Concept Design

[ivconic]

Continuing now with new material...

Based on everything brought up so far there is a clear inclination toward PI, and even CCPI. Further discussion should consider things like power consumption and discrimination, things that should have been explored in the Definition stage. Ferinstance, I know that iron is a problem in some areas, maybe not so much in other areas AFAIK. But a weakness with CCPI is that the reactive signal is incredibly short and not useful for iron ID. It's one area where the GPZ lags the GPX. And in any PI design you have to pay close attention to power consumption. That has barely been mentioned but is important. Finally, whatever we develop has to have excellent ground handling so think about how that would be done in any proposals.

So let's continue figuring out the high-level approach.

Power consumption...
I vote for low current design. Lowest possible.
I am still itched by the design made by White's and named AF108.
I never had it in hands. But looking at its schematic I see lot of interesting but not completely clear parts for me.
It's far different from what we want here... I just have weird urge to mention it...

[Tinkerer]

Power consumption...
I vote for low current design. Lowest possible.
I am still itched by the design made by White's and named AF108.
I never had it in hands. But looking at its schematic I see lot of interesting but not completely clear parts for me.
It's far different from what we want here... I just have weird urge to mention it...

I plan for about 1W TX power consumption

[KingJL]

It is the most versatile TX that I have come across.
I agree.
Do you already have a PCB for that?

Yes, I have an evaluation PCB that I have been using for a couple of months.


I have an upgraded version that should arrive 30 Jan. The new version arriving on the 30th has onboard provisions to configure as CC or half sine using 2 jumpers.

With both of these evaluation boards versions the TX voltage is adjusted by a trimpot. In a final design this would be replaced by a 100K digipot (I2C).

[Carl-NC]

The direction I'm headed in is a multi-period CCPI transmitter with a direct-sampling receiver:



The TX is Moodz' CCC-PI design with a dual period waveform as I proposed here. I would include space for the half-sine cap just for funsies.
The preamp is the differential design proposed by Tony. By shorting the input resistors you get my current-mode version.
The ADC is TBD but needs to be a fast SAR and likely 24 bits. A leading candidate would be the LTC2380 which I already have designed into another direct sampling design.
The micro is TBD but will be a fast (>200MHz) 32-bitter. I personally have a lot of experience with STM and some experience with PIC32.
The TX, preamp, and anti-alias filter could all be placed on one PCB, and mated to an ADC eval board and micro dev board. That allows for easy swapping of the ADC and micro if needed.
Before proceeding, three things need to be done:

1. An analysis of front-end noise and dynamic range, to determine power supplies & ADC.
2. Determine if tilt/offset compensation is necessary (it probably is) and how to do it.
3. Decide how to clock the dual period waveform (either DMA-framed timer, or glue logic; I would include the glue logic but also try to get the software solution working).

I always look for ways to hedge my bets, so I would also consider a secondary analog sampling PCB:


This could pick off the main board preamp signal and has 8 full-wave demod channels. Normally each demod requires 2 clock lines (16 total) but with glue logic you can get it down to 8 clocks + 1 control line (9 total). Two of these boards could be stacked if you need 16 channels.
The ADC is simultaneous sampling 16-24 bits. My experience is with the ADS131E08 (8x24b) but its restrictive sample rate range makes it tough to synchronize. I would look for something easier.

Additional elements needed are:

• Power supplies
• Audio driver
• Display -- at a minimum a 4x20 Hitachi display, for development only
• Inputs for a few pots
• Inputs for some push-buttons

The UI stuff is probably on a separate PCB.

[Willy Bayot]

The direction I'm headed in is a multi-period CCPI transmitter with a direct-sampling receiver:



The TX is Moodz' CCC-PI design with a dual period waveform as I proposed here. I would include space for the half-sine cap just for funsies.
The preamp is the differential design proposed by Tony. By shorting the input resistors you get my current-mode version.
The ADC is TBD but needs to be a fast SAR and likely 24 bits. A leading candidate would be the LTC2380 which I already have designed into another direct sampling design.
The micro is TBD but will be a fast (>200MHz) 32-bitter. I personally have a lot of experience with STM and some experience with PIC32.
The TX, preamp, and anti-alias filter could all be placed on one PCB, and mated to an ADC eval board and micro dev board. That allows for easy swapping of the ADC and micro if needed.
Before proceeding, three things need to be done:

1. An analysis of front-end noise and dynamic range, to determine power supplies & ADC.
2. Determine if tilt/offset compensation is necessary (it probably is) and how to do it.
3. Decide how to clock the dual period waveform (either DMA-framed timer, or glue logic; I would include the glue logic but also try to get the software solution working).

I always look for ways to hedge my bets, so I would also consider a secondary analog sampling PCB:


This could pick off the main board preamp signal and has 8 full-wave demod channels. Normally each demod requires 2 clock lines (16 total) but with glue logic you can get it down to 8 clocks + 1 control line (9 total). Two of these boards could be stacked if you need 16 channels.
The ADC is simultaneous sampling 16-24 bits. My experience is with the ADS131E08 (8x24b) but it's restrictive sample rate range makes it tough to synchronize. I would look for something easier.

Additional elements needed are:

• Power supplies
• Audio driver
• Display -- at a minimum a 4x20 Hitachi display, for development only
• Inputs for a few pots
• Inputs for some push-buttons

The UI stuff is probably on a separate PCB.

Very Nice Synthesis Job

Now that the 'Boss' has done his job, where are we going from here?
Who does what?

[Willy Bayot]

The ADC is TBD but needs to be a fast SAR and likely 24 bits. A leading candidate would be the LTC2380 which I already have designed into another direct sampling design.

I agree about the LTC2380. It seems that the 24-bit version QFN package types are available (small stock at Mouser and Digikey). Its price is rather steep but we only need ONE and this is a critical component in the whole system. MSOP package types (easier to manually solder) are not available.


The micro is TBD but will be a fast (>200MHz) 32-bitter. I personally have a lot of experience with STM and some experience with PIC32.

Choosing one of those also depends on the availabilty of cheap ready-made development boards for the preliminary prototyping and measurement tasks. I know that this is true for various types of STM32 types with the NUCLEO and DISCOVERY boards but I do not know much about devlt boards for the PIC32 (maybe the CURIOSITY PIC32MZ EF 2.0 DEVELOPMENT BOARD, expensive!!).
Since we intend to use Output Compare in rather complex and dynamic timing schemes, I would lean to suggest the PIC32 because its OC features are much easier to dynamically control than the OC of STM32.

Like Carl, I also have a lot of experience with STM32 development on CUBE and some experience with the PIC32MZ and MPLAB.
I can help in the programming the critical capture and DSP code on any of those platforms.

[moodz]

The eval board for the LTC2380 from LTC has a EPM570GT100C4N CPLD on board .... the verilog source code is in the resources for the product ... so it would be a big time saver to go with the eval board .... ;-)

It looks as though there is enough logic resources there to handle some of the data preprocessing ... not exactly DSP but buffering / timing etc.

moodz

[Willy Bayot]

The eval board for the LTC2380 from LTC has a EPM570GT100C4N CPLD on board .... the verilog source code is in the resources for the product ... so it would be a big time saver to go with the eval board .... ;-)

It looks as though there is enough logic resources there to handle some of the data preprocessing ... not exactly DSP but buffering / timing etc.

moodz

WOUW!!!

[Willy Bayot]

About the LTC2380 which is specified capturing at 2Msps, I made a quick calculation taking into account the max clock speed of SPI for the STM32 and the PIC32MZ.

According to the datasheet of the ADC, tCONV = min 343nsec, minimum tACQ = 95nsec for 24 SPI clock periods. with a minimum tCYC of 500nsec (2Msps)

PIC32 max SPI clock speed = 25Mhz or period 40nsec--> tACQ = 40x24 = 960nsec, tACQ+tCONV = 1.3µsec/sample = 770 Msps

STM32 max SPI clock speed = 42Mhz or period 24nsec--> tACQ = 24x24 = 576nsec, tACQ+tCONV = 0.9µsec/sample = 1100 Msps

Thus, in practice, we can expect to get more or less one raw sample every µsec in Direct Sampling mode

[waltr]

We use the LT2380-24 and -20 where I work.

First thing we learned is that the PCB layout and bypass cap placement is VERY CRITICAL to obtain the performance spec'ed.
Biggest was put the ref input cap as close as possible to the ref pin and ground pins. Other wise the Ref droops during acquisition.

We use a PLD (MachXO3) to run SPI at 100MHz for acquisition then to a 32-bit CPU buss.

Great design block so far.
Doing modular for development is necessary.
I see the following Modules:
Front end
Analog acqusition
Timing and logic
CPU/DSP
User interface

Also see each of us maybe trying different approaches, STM32 verse PIC32 or some other processor.

[moodz]

WOUW!!!

yah the devel board is "relatively expensive" ( about USD240 ) where I am ... but ... USD240 would only buy you one hour of consultation with a design engineer and you wouldn't have anything to show except maybe some high level design concepts to show for it.

The board has the source code and the layouts / gerbers ... the engineering is 95% done and you would be hard pressed to build a one off protoboard with similiar components for less. :-)

the ADC7760 board is cheaper ( about USD100 ) it samples at 2.5 msps @ 24 bits or 40 msps @ 16 bits.

Probably wont suit the ppl who like 555s for their function blocks

just sayin

moodz

[Teleno]

The new AI toy ChatGPT can produce code to configure peripherals in Atmega, STM32 etc.

Example:

code in C to configure Timer 1 of an STM32F103C8 to toggle a pin for the last 100us of a 1000us period with an initial pin value of high. Use compare match. Simultaneously, configure Timer1 to trigger the ADC at the first 5us of the aame 1000us period using another compare match. Store the ADC conversion value in a variable "target". Use peripheral register references, avoild STDlibrary, avoid LL library, avoid HAL. Zero latency ADC trigger and pin toggle.

#include "stm32f10x.h"

void configureTimer1(void)
{
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; // Enable clock for TIM1

// Configure compare match to toggle pin at last 100us of 1000us period
TIM1->ARR = 1000 - 1; // Set auto-reload value to 999 (1000us - 1)
TIM1->CCR1 = 1000 - 100 - 1; // Set compare match value to 900 (1000us - 100us - 1)
TIM1->CCMR1 = (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1); // Toggle pin on compare match
TIM1->CCER = TIM_CCER_CC1E; // Enable compare match channel 1
TIM1->EGR = TIM_EGR_UG; // Update registers
TIM1->CR1 = TIM_CR1_CEN; // Start timer

// Configure compare match to trigger ADC at first 5us of 1000us period
TIM1->CCR2 = 5 - 1; // Set compare match value to 4 (5us - 1)
TIM1->DIER |= TIM_DIER_CC2IE; // Enable compare match 2 interrupt
NVIC_EnableIRQ(TIM1_CC_IRQn); // Enable TIM1_CC interrupt in NVIC

// Configure ADC
RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; // Enable clock for ADC1
ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL_1; // Enable ADC, set external trigger, and select TIM1_CC2 as trigger source
ADC1->SQR1 = (ADC_SQR1_L_0 | ADC_SQR1_L_1); // Set 2 conversions in regular sequence
}

void TIM1_CC_IRQHandler(void)
{
if (TIM1->SR & TIM_SR_CC2IF)
{
uint16_t target = ADC1->DR; // Store conversion result

TIM1->SR &= ~TIM_SR_CC2IF; // Clear compare match 2 interrupt flag
}
}
​

[Carl-NC]

Here is a first-cut at noise analysis. I will use a simplified version of Tony's front-end schematic:



To makes things easier I will ignore RL and combine the R1's:



Considering just one opamp, the noise due to the input resistance is



R1=2k and R2=10k so



The feedback resistor R2 (10k) has a noise that is



The opamp (ADA4807) has an input referred voltage noise of 3.1nV/rtHz and its noise gain is (5+1):



The opamp current noise is 10pA/rtHz but splits between R2 in one opamp and 2R1+R2 in the other opamp. This means that most of the current noise is common-moded at the outputs. The difference is



Now we take the squareroot-sum-of-squares to get the total noise. However, this is a differential amp so each vnx term shows up at each output. For an uncorrelated term we can just multiply by sqrt(2) but in the case of vn1 the noises are correlated between the two opamps so it needs to be doubled. So the total differential noise is



This is applied to a difference amp with a gain of 5 so its output noise is 284.2nV/rtHz.

Now we need the noise bandwidth. If we assume we want to respond to a 0.25us target then we need a bandwidth of



Assuming a 1-pole roll-off gives us a NBW multiplier of π/2, or NBW = 1MHz.

The total integrated noise is now



Peak-to-peak noise is ~6x this value, or 1.71mV.

At the ADC input this is 586.5 codes per volt, so a 5V full-scale input would need 2932 codes, or 12 bits. Or, to put another way, for a 16 bit converter @ 5V we have about 22 LSBs of noise. This is not good. I'll stop for now to review these numbers to see if I did something wrong.

[Carl-NC]

I haven't seen any glaring problems with the last post so I'll continue using my current mode approach. Now the input resistance is RL instead of 2R1. For RL I will arbitrarily use 20Ω and to keep the gain the same as before R2 is now 100Ω



The feedback resistor R2 (100) has a noise that is



The opamp noise has not changed:



The opamp current noise still splits with the same ratio:



Same correlation as before so the total differential noise is



This is applied to a difference amp with a gain of 5 so its output noise is 135.0nV/rtHz.

NBW is the same as before so the total integrated noise is now 135uV rms or 809.7uvpp. This is 1235 codes per volt so a 5V full-scale input would need 6175 codes, or 13 bits. Or for a 16 bit converter @ 5V we have about 11 LSBs of noise. This is a little better than before.

By using a low input resistance all the noise terms have been reduced but the opamp noise now dominates. A 1nV/rtHz opamp will knock the vn3 term down to 6nV/rtHz and the overall noise down to 52.1nV/rtHz or 52.1uV rms or 312.6uvpp. This is 4.1 LSBs of noise @ 16 bits which is starting to look pretty decent.

It's looking like a 24b converter is massive overkill and a good 16b ADC will do the job. I may use 18b just to hedge my bets. This will reduce the ADC cost by $20-30.

[waltr]

Very nice noise analysis Carl. I have been leery of the 24bit ADC requirement due to noise. You just showed this to be true.
I still think over sampling with a fast 12bit ADC would work but having extra resolution shouldn't hurt.
.