Concept Design

[Willy Bayot]

The only type (package) that is available in stock from Mouser is :
https://www.mouser.be/ProductDetail/...nv0qaNZg%3D%3D
It costs 62€ as a single unit.
Not many in stock (59) but OK to make experiments.
The only critical component which needs to complement this ADC is a differential ADC driver supporting 24-bit ADC's.
e.g. https://www.mouser.be/ProductDetail/...VkyNgTKw%3D%3D
cost : €7

A voltage reference component is also required since there is no internal reference on that ADC.

In order to make any meaninful experiments, we would need to build a CC-type XMIT circuit and a complete AFE.
We need a basic computing platform as a ready-made developement board to control switching, DMA-based SPI for the ADC and log/record results.
We also need to define and build a suitable coil assembly (XMIT and RECEIVE) choosing between concentric or DD or OO coils.

Stilll many steps before calling this a DETECTOR prototype

[ivconic]

So, only ADC board/module, call it whatever you want; will cost not less than $70 and probably more than that. JLPcb fabrication is not expensive, yet if they are about to source the components... well... i will count on price not bellow $80-90.
And that's only a ADC module.
Well, well...
Ok, let's start from a scratch, let's take LTC2380CDE-24, LMP8350MA and what else and draw the schematic of it.
Voltage reference can be taken from mcu, or not?
Anyway, add voltage reference too on board.
Probably several caps and resistors.
Let's see first complete schematic here, at least of one module.

[Carl-NC]

The noise analysis shows that a 24b ADC is overkill. An 18b ADC is more than enough and a 16b may work. Let's finish the design work before ordering parts.
Currently I'm looking at

• Different ADC families
• Noise analysis to confirm calculations
• How to deal with flicker noise

[waltr]

Yes, the LTC2380-24 is over $60US. There is a LTC2380-20 (20-bit) that is a bit less money.
We uses both of these on the instruments we design where I work. The ADC circuit can be about 20 x 20mm plus Reference circuit about the same size.
Design and Layout of both are critical.

As to most Eval Boards; these are typically much larger than needed when integrated into a project. (example of ADC I mentioned).
PLD (Programmable Logic Devices of any kind) eval boards typically are large due to pinning out everything to connectors. Actual PCB real estate typically is about twice the area of chip's footprint mostly due to by-pass caps and traces/vias to route to the PLD.

[moodz]

..below is the first Kodak digital camera prototype. Nowadays you can buy a single chip camera.

It does not matter what size or chips the first prototype uses ... so long as the POC ( proof of concept ) demonstrates the desired features then like natural selection in nature the fittest will survive ( and evolve ).

For those who dont have 24/18/16 bit ADCs with powerful CPU attached ... it would / will be great to have a 24/18/16 bit board general purpose board that could sit at the heart of this project and maybe others.

I am using FPGA and AD7760 because I have them to hand .... but the step of creating / selecting a 24 bit ADC/CPU is only a step its not the end goal .. so I am starting to move to the next step which is assembling an AFE and CC RX/TX .. which will ( probably ) not be on a nice PCB either.

Not really worrried if the POC is the size of a shoebox I have made plenty of really small projects that didnt work properly in my career as well

Just a thought ..

moodz

[Willy Bayot]

..below is the first Kodak digital camera prototype. Nowadays you can buy a single chip camera.

It does not matter what size or chips the first prototype uses ... so long as the POC ( proof of concept ) demonstrates the desired features then like natural selection in nature the fittest will survive ( and evolve ).

For those who dont have 24/18/16 bit ADCs with powerful CPU attached ... it would / will be great to have a 24/18/16 bit board general purpose board that could sit at the heart of this project and maybe others.

I agree, the experimental system should preferably be modular (made of several functional modules) without consideration of the size of the system and its packaging, this will come later on.

The CPU does not need to be so powerful, what is important here is the clock rate of its SPI link if the ADC to be used is serially connected and a good DMA support for the SPI to make full use of its sampling rate.

[Willy Bayot]

Yes, the LTC2380-24 is over $60US. There is a LTC2380-20 (20-bit) that is a bit less money.
We uses both of these on the instruments we design where I work. The ADC circuit can be about 20 x 20mm plus Reference circuit about the same size.
Design and Layout of both are critical.

As to most Eval Boards; these are typically much larger than needed when integrated into a project. (example of ADC I mentioned).
PLD (Programmable Logic Devices of any kind) eval boards typically are large due to pinning out everything to connectors. Actual PCB real estate typically is about twice the area of chip's footprint mostly due to by-pass caps and traces/vias to route to the PLD.

It is indeed an expensive component of the system (even more than the CPU) but it is maybe THE most critical part of the whole data processing sub-system in DIRECT SAMPLING mode. After all, we only need ONE.
My point of view would be to make the first experiments on a single system (a guinea pig) with a 24-bit ADC and possibly downgrade it later if we really find that it was an overkill.
Starting the experiments wih a 18-bit or 16-bit ADC could end up with a receive chain and its digital integration giving not enough SNR in DIRECT SAMPLING mode.
We must remember that the digital integration has a limit defined by the ratio between the pulse period and the acceptable rate of net audio feed-back. If the pulse period is let's say 100µsec, the maximum digital integration is x100 if you want an audio responses every 10msec (or 10mm @ swing speed of 1 m/sec)

[ivconic]

..below is the first Kodak digital camera prototype. Nowadays you can buy a single chip camera.
It does not matter what size or chips the first prototype uses ... so long as the POC ( proof of concept ) demonstrates the desired features then like natural selection in nature the fittest will survive ( and evolve ).
For those who dont have 24/18/16 bit ADCs with powerful CPU attached ... it would / will be great to have a 24/18/16 bit board general purpose board that could sit at the heart of this project and maybe others.
I am using FPGA and AD7760 because I have them to hand .... but the step of creating / selecting a 24 bit ADC/CPU is only a step its not the end goal .. so I am starting to move to the next step which is assembling an AFE and CC RX/TX .. which will ( probably ) not be on a nice PCB either.
Not really worrried if the POC is the size of a shoebox I have made plenty of really small projects that didnt work properly in my career as well
Just a thought ..
moodz

Please don't misunderstand, I had no objections to what is seen in your photos, on the contrary; I envy you because you have it and I don't.
I was just pointing out that the final "product" needs to be much more compact and will be desirable; on as fewer pcbs as possible.
I remembered the Garrett GTI 2500, it's a very nice and well packaged machine.
Same as GTI1500:



In that manner, we could also plan this detector.
As for ADC... long before the idea of this project even came up; I've been trying for a long time to find a good solution for a universal ADC module,
which will have everything I need and which will be useful in my workshop for various experiments.
So all this is not empty talk. Even if I don't finish the detector, for one reason or another; I would like to have at least one such ADC module
and one "universal" RX and TX module for various bench experiments.
And I've already made something by now. But it's hard to decide because something better and more advanced always comes along.
The big problem is that I can't provide anything serious on those topics here locally.
Money is a problem and not a problem. Because some things are bought only once.
It is not a problem to pay $100 if the module will be used for a long time to develop various devices.
But the problem is with delivery to my country, everything over 70e value is subject to customs.
And that is already a problem, not only because of the higher price at the end, but also because of the great loss of time.
The domestic producer "Mikroelektronika" has a lot to offer, but the prices are astronomical!
Stalemate situation.

[moodz]

It is indeed an expensive component of the system (even more than the CPU) but it is maybe THE most critical part of the whole data processing sub-system in DIRECT SAMPLING mode. After all, we only need ONE.
My point of view would be to make the first experiments on a single system (a guinea pig) with a 24-bit ADC and possibly downgrade it later if we really find that it was an overkill.
Starting the experiments wih a 18-bit or 16-bit ADC could end up with a receive chain and its digital integration giving not enough SNR in DIRECT SAMPLING mode.
We must remember that the digital integration has a limit defined by the ratio between the pulse period and the acceptable rate of net audio feed-back. If the pulse period is let's say 100µsec, the maximum digital integration is x100 if you want an audio responses every 10msec (or 10mm @ swing speed of 1 m/sec)

Absolutely right ... starting at 18 or 16 bits may result in "ADC regret" afterwards. To underline that point I have been thinking about the ADC processing and timing playing with the AD7760. ( dont worry Ivconic ...its only a tool for exploring ).

So I have set the sampling to 2.5 MSPS continuous ( as if you use the sync input it resets the internal FIR and glitches the data till the device settles ) and the FPGA bins 512 samples in a dual port ram oversampling by 4096 ( 12 bits for 6 bits of oversampling gain) in each bin
so dividing the 2.5 SMPS by 512 samples gives the total sampling period ( corresponding to the RX/TX period of the detector ) of 4.8828125 Khz which is 204.8 microseconds .. quite handy for detecting type timings.
By doing this I have the equivalent of 512 sampling integrators evenly spaced across the TX and RX period at every 0.4 microseconds. The o/p from each of the 512 bins or integrators is at 2.5 MSPS/4096 = 610.35 hz ... well above the required rate to resolve targets in a timely manner.

Of course you can set up other timings dependant on the ADC sample rate.

The noise floor on the output integrators is below a few microvolts peak ... before sampling and integration in the order of 100s microvolts ... very pleased.

It appears to have sub microvolt sensitivity :-)

moodz.

[moodz]

Absolutely right ... starting at 18 or 16 bits may result in "ADC regret" afterwards. To underline that point I have been thinking about the ADC processing and timing playing with the AD7760. ( dont worry Ivconic ...its only a tool for exploring ).

So I have set the sampling to 2.5 MSPS continuous ( as if you use the sync input it resets the internal FIR and glitches the data till the device settles ) and the FPGA bins 512 samples in a dual port ram oversampling by 4096 ( 12 bits for 6 bits of oversampling gain) in each bin
so dividing the 2.5 SMPS by 512 samples gives the total sampling period ( corresponding to the RX/TX period of the detector ) of 4.8828125 Khz which is 204.8 microseconds .. quite handy for detecting type timings.
By doing this I have the equivalent of 512 sampling integrators evenly spaced across the TX and RX period at every 0.4 microseconds. The o/p from each of the 512 bins or integrators is at 2.5 MSPS/4096 = 610.35 hz ... well above the required rate to resolve targets in a timely manner.

Of course you can set up other timings dependant on the ADC sample rate.

The noise floor on the output integrators is below a few microvolts peak ... before sampling and integration in the order of 100s microvolts ... very pleased.

It appears to have sub microvolt sensitivity :-)

moodz.

Adding to this ... forgot ... because the 4096 oversample is for EACH sample point the noise is further spread over the 512 integration / bin points ... so we get a processing gain ( think of spread spectrum ) of at least 3 bits so the total bit gain is 12 + 3 say to get 15 bit oversampling on 24 bits.
The effective sample rate of each integrator is 610 Hz so there is still headroom for more filtering and still have an adequate target response.
Here is the open circuit noise on the ADC at maximum resolution. Each pixel is a voltage unit well under a microvolt. It picks up my hand at just on 10 cm from the input connetor with a couple inches of wire ..open circuit.

The two red spikes are markers ( I set one of 512 integrators to a fixed value ) and thus the display "wraps around" with 511 integration points between each marker ... The period between the markers is 204.8 microseconds.



Full scale noise ...

[moodz]

Adding to this ... forgot ... because the 4096 oversample is for EACH sample point the noise is further spread over the 512 integration / bin points ... so we get a processing gain ( think of spread spectrum ) of at least 3 bits so the total bit gain is 12 + 3 say to get 15 bit oversampling on 24 bits.

.... my bad ... the oversampling gain is 6 + 3 = 9 bits not 15 bits. The ADC prob only gets 20 noise free bits on a good day so maybe were getting 20 + 9 = 29 bits of goodness ... still bloody excellent.

moodz

[ivconic]

Purely for entertainment and education; use the same math and explain direct sampling with Deus.
VLF I/B, direct sampling, for Deus we already know that it works very well and very accurately.
With the VLF I/B detector, the complete sine is digitally reconstructed, and further filters process the phase and amplitude.
In PI detectors with direct sampling, only part of the signal immediately after the main pulse is digitally reconstructed. The decay part.
If we compare these two types of direct sampling; layman's question: in which do we have more data for further processing?
Personally, I see no reason to digitally reconstruct the complete duration of the pulse and later the decay period.
Except in the case of using a searchead with two coils.
And even then, I don't see how anything useful will be extracted from the part of the reconstructed signal that is "overlaid" by the pulse duration.
If we assume that the width of the main pulse is 100uS (up to 200uS makes sense); what will happen in RX coil during that time?
The target response will be completely covered by the main pulse.
We are interested here in the first and few following uS's after the main pulse is turned off.
With the condition that the morphology of the coils and fast recovery RX frontend allows such early sampling.
Simply; it would be good to use mathematics to compare the two cases and prove which one processes more data.
I know little about PI technology, I only know some basics from the "old days".
I didn't follow what new ML was doing, I didn't follow the new techniques that were found.
So, with this example, I might learn things that are not clear to me.
Also, when it comes to ADC conversion, I'm only familiar with the basics.
The basis of the basic definition of analog-digital conversion is the effort to reproduce a signal at the input of the ADC as faithfully as possible.
To convert analog voltage into digital states.
And the more of those digital states are generated from the analog signal; the higher the conversion resolution.
If the signal is "simple" and we do excessive sampling (too high resolution); we will get a bunch of unwanted artifacts in the resulting digital signal.
Then we have the problem of removing those artifacts from the digital signal.
And of course there is the unavoidable noise. Either internal or external.
With an increase in the number of samples on the signal; the number of noise samples also increases.
Now the question arises here; what is the optimal solution. And what amount of data from such a signal is essentially really needed?
In layman's terms, I understand it like this; when the main pulse is switched off, the decay period starts immediately.
And then direct sampling should be started. And do direct sampling until the moment when it makes sense.
If we're looking for the golden nugget and if we've accepted that a TC of 1uS is the time when the most important data for us starts...
how much more after that time does the ADC need to run?
Here are a couple of layman's thoughts and a detailed explanation about this would be very educational, as for me; so, I believe, for the vast majority of those interested here.
I believe that the shame is not in ignorance but in silence and lack of motivation to ask publicly in the desire to learn and overcome the ignorance.

[Willy Bayot]

Look at this post
https://www.geotech1.com/forums/foru...129#post409129
You can see that the first few µsec of decay are not the only parts that tells something about the targets.

[ivconic]

Look at this post
https://www.geotech1.com/forums/foru...129#post409129
You can see that the first few µsec of decay are not the only parts that tells something about the targets.

I saw it and it is splendid post, touches some of my questions.
Before I saw that post again, now when you pointed me on it; I was going to propose direct sampling on only first 30uS of the decay.
Because we will looking for small gold nuggets, that's the main role of our detector here.
Anything above 30uS is far out of our interest here. Or am I wrong?
Even those 30uS are negotiable, maybe we could "chirp" even few uS less than that.
Which left us not so much data to process further, don't you agree?
So the question repeats; in which case we will have more data to process; Deus case with complete sine reproduced or here with only 30uS decay reproduced?
If you don't agree on my proposed 30uS; ok, lets put in math all 85uS from that post.

[Willy Bayot]

'And what amount of data from such a signal is essentially really needed?
If we're looking for the golden nugget and if we've accepted that a TC of 1uS is the time when the most important data for us starts...
how much more after that time does the ADC need to run?

Look at this post
https://www.geotech1.com/forums/foru...129#post409129

If you only care about target DETECTION, you can indeed concentrate on the very first few µsec of the decay just after the damping.
Small low conductivity targets like small nuggets have a very short TC, thus, you must catch the deltas between the ground and target signal as soon as possible.
There are some tricks used to extend this decay in order to catch the short TC more easily (see posts of Moodz)

You can also see that the first few µsec of decay are not the only parts that tells something useful about the material, shape and weight of targets with higher TC values.

However, the decay extending techniques distort the exponential decay and you loose the capability to catch the supplementary decay features loosing ground balance and discrimination capabilities.

On this particular application of nugget hunting, we must be able to detect the small nuggets but also reject the ferrous targets and adapt to difficult ground conditions.

That is the reason why recording the whole decay period in as many narrow slots as possible is important in Direct Sampling mode. Then, the DSP can process these one by one or by grouping them.

see post #129 of Moodz:
By doing this I have the equivalent of 512 sampling integrators evenly spaced across the TX and RX period at every 0.4 microseconds. The o/p from each of the 512 bins or integrators is at 2.5 MSPS/4096 = 610.35 hz ... well above the required rate to resolve targets in a timely manner.