Barracuda Legend Kit Problems

[raygdunn]

Can someone please probe pin8 of the 40106 with a scope on channel 1, and then pins 12, 6, 4 and 2 respectively, so that we can see the relationship between the TX oscillator output (pin 8 ) and each of these signals.

I can see that running the 40106 between 0V and -5V will drive the TX stage correctly, but I'm not certain about the main and EFE samples. Clearly, several people have already built this design and claim that it works, so is there a discrepancy between the schematic and the actual board? There's something a but fishy here that needs to be clarified.

Hi Qiaozhi,

As I'm set up for the job...

(I kept to same scale here. I can redo if you need the full second sample pulse.)


(This is with the supply mod of earlier today reversed out)

Let me know if they are not quite what you had in mind.

Ray

[Qiaozhi]

Hi Qiaozhi,

As I'm set up for the job...
[ATTACH]35560[/ATTACH]
[ATTACH]35561[/ATTACH] (I kept to same scale here. I can redo if you need the full second sample pulse.)
[ATTACH]35562[/ATTACH]
[ATTACH]35563[/ATTACH]
(This is with the supply mod of earlier today reversed out)

Let me know if they are not quite what you had in mind.

Ray

Thanks Ray.
These all look as you would expect, so clearly the circuit is working.
Main sample delay ~40us
Main sample pulse ~40us
EFE sample delay ~180us
EFE sample pulse (cannot see width, but assume this must be ~40us)

Can you confirm that the circuit is wired up as per the attached schematic with the CD40106 connected with VDD=0V and VSS=-5V?

[Old cart]

Thanks Ray.
These all look as you would expect, so clearly the circuit is working.
Main sample delay ~40us
Main sample pulse ~40us
EFE sample delay ~180us
EFE sample pulse (cannot see width, but assume this must be ~40us)

Can you confirm that the circuit is wired up as per the attached schematic with the CD40106 connected with VDD=0V and VSS=-5V?
[ATTACH]35564[/ATTACH]

Not to speak out of order but that is the way his supplies are arranged. See how r17,18 and 19 are pulled up to 5 V? This pulls the input pins on some chips to go above .5v. This exceeds to mfg specs on the parts. Some chips seem to be able to survive this, others start generating runt pulses like those seen in post 288. Once they break they break, they never work right again. It is my suspicion it is due to this input abuse. Some of the early Baracuda schematics showed the pins pulled of to VDD but never stated it was plus 5. It is hard to tell from the original Barracuda photos but it looks like the wiring is to +5. I believe the designer made a mistake and that was never revealed because the chips he used were just more tolerant.
Does this seem plausible?

[6666]

Some of the early Baracuda schematics showed the pins pulled of to VDD but never stated it was plus 5.

On the Nov 2002 schematic which has some mistakes, it shows VDD to be +5 volts from a +5v reg

and on the Rev D schematic it shows +V as +5 volts from a plus 5v reg. (very old cct)

I have a NXP brand IC in my Bara. seems ok so far.

[Impulse]

Hey guys i have put the barracuda away for now as i picked it up to test the shielding on/off and the movement issue has come back? i haven't taken the shield off NOTHING changed! i simply cant keep going with something that does NOT work.
Is there some one out there that i could send this thing to? that would be willing to have a look? as there must be something majorly wrong with what i am doing

[Qiaozhi]

Hey guys i have put the barracuda away for now as i picked it up to test the shielding on/off and the movement issue has come back? i haven't taken the shield off NOTHING changed! i simply cant keep going with something that does NOT work.
Is there some one out there that i could send this thing to? that would be willing to have a look? as there must be something majorly wrong with what i am doing

In which country do you live?
If it's the UK, you can send it to me.

[Qiaozhi]

On the Nov 2002 schematic which has some mistakes, it shows VDD to be +5 volts from a +5v reg

and on the Rev D schematic it shows +V as +5 volts from a plus 5v reg. (very old cct)

I have a NXP brand IC in my Bara. seems ok so far.

The Baracuda PCB, supplied by Silverdog, was designed by Apberg.
Can someone post the schematic that corresponds to that particular board?

[Impulse]

In which country do you live?
If it's the UK, you can send it to me.

I live in kent near dover. It would be great to send it to you and find out what I'm doing wrong with it.

[Qiaozhi]

I live in kent near dover. It would be great to send it to you and find out what I'm doing wrong with it.

OK - I'll send you a PM.

[ivconic]

The Baracuda PCB, supplied by Silverdog, was designed by Apberg.
Can someone post the schematic that corresponds to that particular board?

Closest would be "Attachment 35162" from #324.
I checked it partially with my pcb.
So far i haven't found mistakes.

[Qiaozhi]

Closest would be "Attachment 35162" from #324.
I checked it partially with my pcb.
So far i haven't found mistakes.

Thanks. Got it!

[kt315]

If your timing resistor ties to +5V you will be outside the chips reference of -5 to 0.

CMOS chips do not like that.

So maybe that's why the latchup would occur?

why?? CMOS CD4000B series have 20V max rating and 10V is OK for them (with the timing resistors connected to +5). i do not see something wrong here.
yes, that seems unusually but perfectly acceptable.

[raygdunn]

Closest would be "Attachment 35162" from #324.
I checked it partially with my pcb.
So far i haven't found mistakes.

Thanks. Got it!

Hi Qiaozhi,

The only differences that I can spot are minor: a buzzer rather than a headset socket; a 20K pot replacing both R27 and R29. (My R21 was 390 rather than 330ohms, but another post suggested this was not usual).

It would be wonderful if this was added to the Sticky, tagged as the Silverdog kit version. I gave up trying to read the hand drawn schema in the zip file. It is just not a very clear digital copy.

I failed to pick out this schema to work with, instead picking the latest posted. The differences were very confusing, but ultimately I've learnt more.☺

Ray

[Old cart]

why?? CMOS CD4000B series have 20V max rating and 10V is OK for them (with the timing resistors connected to +5). i do not see something wrong here.
yes, that seems unusually but perfectly acceptable.

KT the max voltage rating is NOT the problem. It is the Input voltage range. In this application the maximum voltage on the power pins is 0 volts. This design pulls 3 of the inputs to about .5volts or a little higher. Basically this causes the input protection diodes to turn on hard. After some time these diodes break down and this causes the chip to generate spikes. Not al chips do this, only some brands and variations.

Some brands are not destroyed. The fact that it works most of the time is just luck. But this is bad design practice and should be avoided.

Several people have made note that their Barracuda's work fine. I do not argue that some, if not most of them do. But clearly some work only for a while then break.

Final note- I really have no idea what is actually going on inside the chip because I do not have an electron microscope but it seems plausible...

[raygdunn]

Thanks Ray.
These all look as you would expect, so clearly the circuit is working.
Main sample delay ~40us
Main sample pulse ~40us
EFE sample delay ~180us
EFE sample pulse (cannot see width, but assume this must be ~40us)

Can you confirm that the circuit is wired up as per the attached schematic with the CD40106 connected with VDD=0V and VSS=-5V?
[ATTACH]35564[/ATTACH]

Yes standard wiring. I reversed out the mod for the job... Also to confirm the old delay timings on the samples. ☺

Ray