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I am counting (or guessing) instruction cycles to get an estimate of the processing load and to figure out what processing device I can use.
It looks like the interrupt overhead just to save and restore essential data is about 20 cycles per interrupt. 20 * 26,400 is 528,000 cycles per sec, which is more than half the throughput of the 4 MHz chips. I don't have to do any more math than this to see that the 4 MHz parts are not fast enough for a 26400 Hz interrupt rate in this project. So I will assume I am using a 20 MHz chip.
By counting and guessing I get:
20 cycles overhead
20 cycles maintaining counters and figuring out what to do on this interrupt
10 cycles controlling the transmit signal
subtotal: 50 cycles every interrupt
In addition there is extra work every 3rd interrupt:
10 cycles read A/D and start next conversion
55 cycles median filter
10 cycles accumulate result
subtotal: 75 cycles every 3rd interrupt
Total for interrupts: 50 * 26,400 + 75 * 8,800 = 1,980,000 or 40% of the throughput of the 20 MHz chip. Assume I forgot something and round this up to 50% of the chip's capacity for the fast loops. That leaves the other 50% for the 60 Hz loop. That is 2,500,000 / 60 = 41,666 cycles available per 60 Hz loop. I have not started adding up cycles in the slow loop but 41k is a number I feel comfortable working with.
I can also see that if I can really get all the work done in the long (3rd) interrupt and have time to set up a few flags I can skip the 20 cycles of overhead on the short interrupts because I can test bits and set bits without altering W or the status flags, So as long as I can get things set up ahead of time my short interrupts can be shorter than I estimated above. That gives me a little safety margin.
But in figuring this out I ran into a couple of problems. While looking at the number of bits required I decided that I wanted to use a 12 bit A/D not 10. Then when I went to look up the part number, I could not find any chip with flash memory and a 12 bit A/D.
I also noticed when looking at the A/D timing that it has a 5 micro sec amplifier settling time. Since I am sampling a 6600 Hz sine wave, it is not going to stay still for 5 micro sec. That means that when I issue the command to open the sample and hold switch and start a conversion, the A/D amplifier is still going to be settling while it is converting the first couple of bits. That will produce bad data, but I cannot estimate how bad. I could not find any spec on what frequencies or slew rate this A/D can handle. If I have to add an external sample and hold it is going to kill some of the appeal of using this "all in one" chip.
Robert Hoolko
It looks like the interrupt overhead just to save and restore essential data is about 20 cycles per interrupt. 20 * 26,400 is 528,000 cycles per sec, which is more than half the throughput of the 4 MHz chips. I don't have to do any more math than this to see that the 4 MHz parts are not fast enough for a 26400 Hz interrupt rate in this project. So I will assume I am using a 20 MHz chip.
By counting and guessing I get:
20 cycles overhead
20 cycles maintaining counters and figuring out what to do on this interrupt
10 cycles controlling the transmit signal
subtotal: 50 cycles every interrupt
In addition there is extra work every 3rd interrupt:
10 cycles read A/D and start next conversion
55 cycles median filter
10 cycles accumulate result
subtotal: 75 cycles every 3rd interrupt
Total for interrupts: 50 * 26,400 + 75 * 8,800 = 1,980,000 or 40% of the throughput of the 20 MHz chip. Assume I forgot something and round this up to 50% of the chip's capacity for the fast loops. That leaves the other 50% for the 60 Hz loop. That is 2,500,000 / 60 = 41,666 cycles available per 60 Hz loop. I have not started adding up cycles in the slow loop but 41k is a number I feel comfortable working with.
I can also see that if I can really get all the work done in the long (3rd) interrupt and have time to set up a few flags I can skip the 20 cycles of overhead on the short interrupts because I can test bits and set bits without altering W or the status flags, So as long as I can get things set up ahead of time my short interrupts can be shorter than I estimated above. That gives me a little safety margin.
But in figuring this out I ran into a couple of problems. While looking at the number of bits required I decided that I wanted to use a 12 bit A/D not 10. Then when I went to look up the part number, I could not find any chip with flash memory and a 12 bit A/D.
I also noticed when looking at the A/D timing that it has a 5 micro sec amplifier settling time. Since I am sampling a 6600 Hz sine wave, it is not going to stay still for 5 micro sec. That means that when I issue the command to open the sample and hold switch and start a conversion, the A/D amplifier is still going to be settling while it is converting the first couple of bits. That will produce bad data, but I cannot estimate how bad. I could not find any spec on what frequencies or slew rate this A/D can handle. If I have to add an external sample and hold it is going to kill some of the appeal of using this "all in one" chip.
Robert Hoolko