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Setting up an interrupt routine to drive the coil and sample the A/D was a little more difficult than I had anticipated. I originally talked about a 26400 Hz interrupt rate to drive the coil and sampling the A/D on every third interrupt. That was a worst case scenario, I was expecting to be able to do better. One reason for choosing the chip I did was because it has 3 timers, 2 of which can be used as PWM's. I thought that I could use one PWM for audio, the other PWM to drive the coil and the timer for the A/D. This way I might get by with 8800 or at worst 8800 + 6600 interrupts per sec instead of 26400. But I ran into problems.
For one thing the PWM's did not work the way I expected. You cannot set them to any arbitrary period. The period is only adjusted by powers of 2, and you cannot get from 8 MHz to 6600 Hz using powers of 2. I would need a 6.76 MHz crystal. But even if I had that crystal there is a problem with interrupt priorities. The coil drive rate and sampling rate must be an exact 4:3 ratio and there cannot be any jitter in either one or it will result in noisy data. So I can only use the timer that has the highest interrupt priority for coil drive and sampling. And the highest priority timer is not the most versatile one. It is an 8 bit timer with one compare register.
I wound up using the timer in compare mode and reloading the timer, the compare register, and the mode on every interrupt. In compare mode the timer can change an I/O bit when the timer matches the compare register. I was able to drive the coil and read the A/D in a sequence of six interrupts spanning 3 cycles of the transmit signal. That is a rate of 13200 per sec.
I will label the quadrants of those three cycles as Q0 through Q11. Q12 would be Q0 of the next three cycles. a quadrant is 90 degrees. I need to drive the coil on every 4th quadrant and read the A/D on every 3rd. This gets me an A/D every 270 degrees and takes 3 cycles to get a full set of data. The system is not fast enough to take a sample every 90 degrees. I want the coil drive pulses to be centered on Q0, Q4, and Q8. They should be centered so there will not be a phase shift if I change the drive pulse width. The A/D will be sampled at Q0, Q3, Q6, Q9. So interrupts have to occur at Q0, Q3, Q4, Q6, Q8, Q9. Those are the 6 interrupts. On each interrupt I have to set the timer interval for the next interrupt, set the compare register to the time at which I want the drive current to turn on or off, and set the mode to control whether the drive current turns on or off at the next compare.
This is a table of what happens in the interrupt
I Q A T C M
-------------------
1 0 1 3 w off
2 3 1 1 t-w on
3 4 0 2 w off
4 6 1 2 t-w on
5 8 0 1 w off
6 9 1 3 t-w on
The table columns are Interrupt, Quadrant, A/D, Timer, Comparator, Mode. w is 1/2 the drive pulse width, t is the time to the next interrupt.
Reading the first row: interrupt 1 occurs at Q0, sample the A/D, set timer interval to 3 quadrants, and set the comparator to turn the drive current off after w time units. In the second row the drive current is turned on at t-w, that is, at w units before the next interrupt.
Looking at rows 6 and 1 you can see that interrupt 6 turns the drive current on w units before the next interrupt at Q0 and interrupt 1 turns the current off w units after Q0. The drive pulse is 2w centered on Q0. The same thing happens around Q4 and Q8.
I have a test version of this routine running. It looks very stable on the scope. The execution time is about 5.5 usec when there is no A/D and about 9.5 when there is. This works out to about 11% of the chip's throughput at 8 MHz, but I am not doing any filtering yet.
Robert Hoolko
For one thing the PWM's did not work the way I expected. You cannot set them to any arbitrary period. The period is only adjusted by powers of 2, and you cannot get from 8 MHz to 6600 Hz using powers of 2. I would need a 6.76 MHz crystal. But even if I had that crystal there is a problem with interrupt priorities. The coil drive rate and sampling rate must be an exact 4:3 ratio and there cannot be any jitter in either one or it will result in noisy data. So I can only use the timer that has the highest interrupt priority for coil drive and sampling. And the highest priority timer is not the most versatile one. It is an 8 bit timer with one compare register.
I wound up using the timer in compare mode and reloading the timer, the compare register, and the mode on every interrupt. In compare mode the timer can change an I/O bit when the timer matches the compare register. I was able to drive the coil and read the A/D in a sequence of six interrupts spanning 3 cycles of the transmit signal. That is a rate of 13200 per sec.
I will label the quadrants of those three cycles as Q0 through Q11. Q12 would be Q0 of the next three cycles. a quadrant is 90 degrees. I need to drive the coil on every 4th quadrant and read the A/D on every 3rd. This gets me an A/D every 270 degrees and takes 3 cycles to get a full set of data. The system is not fast enough to take a sample every 90 degrees. I want the coil drive pulses to be centered on Q0, Q4, and Q8. They should be centered so there will not be a phase shift if I change the drive pulse width. The A/D will be sampled at Q0, Q3, Q6, Q9. So interrupts have to occur at Q0, Q3, Q4, Q6, Q8, Q9. Those are the 6 interrupts. On each interrupt I have to set the timer interval for the next interrupt, set the compare register to the time at which I want the drive current to turn on or off, and set the mode to control whether the drive current turns on or off at the next compare.
This is a table of what happens in the interrupt
I Q A T C M
-------------------
1 0 1 3 w off
2 3 1 1 t-w on
3 4 0 2 w off
4 6 1 2 t-w on
5 8 0 1 w off
6 9 1 3 t-w on
The table columns are Interrupt, Quadrant, A/D, Timer, Comparator, Mode. w is 1/2 the drive pulse width, t is the time to the next interrupt.
Reading the first row: interrupt 1 occurs at Q0, sample the A/D, set timer interval to 3 quadrants, and set the comparator to turn the drive current off after w time units. In the second row the drive current is turned on at t-w, that is, at w units before the next interrupt.
Looking at rows 6 and 1 you can see that interrupt 6 turns the drive current on w units before the next interrupt at Q0 and interrupt 1 turns the current off w units after Q0. The drive pulse is 2w centered on Q0. The same thing happens around Q4 and Q8.
I have a test version of this routine running. It looks very stable on the scope. The execution time is about 5.5 usec when there is no A/D and about 9.5 when there is. This works out to about 11% of the chip's throughput at 8 MHz, but I am not doing any filtering yet.
Robert Hoolko