Gday Tinkerer ... thanks for your reply .. in a professional design I would use a separate drive for the bias generator as the present circuit configuration is highly dependant on a fast pulse repetition rate ( eg > 4 Khz ) to maintain low ripple in the bias generator outputs.
C6 an C7 are actually 10 uf ... I was surprised too that the impact on gate drive timing was so minimal ... the caps dont really have time to discharge much between pulses ( approx 70 mv across 200us ). The diff amp only draws around 10 ma from the supply.
I do hope to get onto descrimination on the FPGA project .... I just need to finalise the dspic code for the Model T demonstrator ( which wont have descrimination )
Regards,
moodz.
C6 an C7 are actually 10 uf ... I was surprised too that the impact on gate drive timing was so minimal ... the caps dont really have time to discharge much between pulses ( approx 70 mv across 200us ). The diff amp only draws around 10 ma from the supply.
I do hope to get onto descrimination on the FPGA project .... I just need to finalise the dspic code for the Model T demonstrator ( which wont have descrimination )
Regards,
moodz.
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