FPGA based UNIPI system

[moodz]

Announcing the FPGA based UNIPI system ( I call it a system because it has more than 1 chip ).

Brief hardware specs

6 X 24 bit ADC channels ( independant not multiplexed ) with programmable gain amplifiers and differential inputs.
6 X 12 / 24 bit DAC depending on required resoution.
4 X rotary encoder controls
Pushbuttons.

Embedded Z80 cpu running at equivalent of 160 Mhz ( Blast from the past )
Serial RS232 port
Hi Speed SPI port ( master / slave )
64 voice audio synthesiser
32K RAM/ROM with outboard 8Mb of ram for hardware use.
4 Transmit pulse generators ( multi pulse capable and full editing of timing waveform )
8 Sample pulse generators ( multi pulse capable and full editing of timing waveform )
10 ns resolution on all timings.
VGA interface ( option ) for bench configuration and testing.
LCD display controller.

Software specs

All the funtionality of the UNIPI chip and more.
Clone-o-matic function .... will copy the timing of another detector by "listening" to the pulse train by holding search head near other detector search head. This copy can then be tweaked by the user.

Documented hardware interface so you can develop your own circuits ( front ends etc ).

moodz.

[hdphilip]

hi moodz,

wow,

just curious, are the ADC and the DAC converters contained on the fpga? or would they be on some sort of interface board?

also, would the LCD be a graphic type, such as a 128x64?

Philip

[moodz]

hi moodz,

wow,

just curious, are the ADC and the DAC converters contained on the fpga? or would they be on some sort of interface board?

also, would the LCD be a graphic type, such as a 128x64?

Philip

The CPU + memory ( rom and ram ) and the hardware for the serial ports, spi, rotary encoders, sound generator, pushbutton debounce, VGA and DAC / ADC interface clocking and pulse generators are all in the one FPGA chip.
You are right, the actual ADC / DACs etc are on the front end board. The DACs connect to the FPGA via a 10 mbit SPI bus ( serial ).

The LCD is the 2x16 char to start with ( as per UNIPI chip ) however a dot matrix type is pretty much no more complexity.


moodz.

[hdphilip]

hello moodz,

i was thinking about your fpga project, would you be able to has a inductance meter built in? in order to be able to do some diagnostics, and help in building different type of search coils. with that in mind, would it also incorporate an "auto-tune" feature that would optimize the timing with a known reference material,
and a battery voltage readout.

what development platform do you plan on using for your project?

Philip

[moodz]

hello moodz,

i was thinking about your fpga project, would you be able to has a inductance meter built in? in order to be able to do some diagnostics, and help in building different type of search coils. with that in mind, would it also incorporate an "auto-tune" feature that would optimize the timing with a known reference material,
and a battery voltage readout.

what development platform do you plan on using for your project?

Philip

Hi Philip,
The inductance meter is a good idea ... it could help out with coil experiments / diagnostics. I have code to to do it for a standalone meter so I should be able to integrate it. Auto tune / balance is definitely on the list. Battery meter also.

The development platform is XILINX ISE webpack for the FPGA system and SDCC for the Z80 cpu control code.

moodz.

[tjmlena]

Im interested.... I will follow you

[bklein]

This is an interesting idea.
What if you go even further and do something like having selectable turns in the coil along with selectable parallel capacitance for resonance tuning. Sort of like a ham antenna tuner... I am curious about reducing coil inductance but increasing resonance and perhaps time-based gain profile of the preamp.

[moodz]

...this project has been sitting on my todo list for over 10 years now. So I got out the development board and blew the dust off .. loaded up the Xilinx webpack software ... downloaded my archive .. tweaked some code and voila : UNIPI lives.
The ADC is a 24 bit AD7760 sampling at 1.25 MSPS over a 512 sample window that implents a running sum of each sample 1024 times into a dual port RAM for a 5 bit resolution improvement ...
The AD7760 is syncronously driven by a XILINX Spartan 3A FPGA.

The FPGA also is programmed to provide an embedded simple oscilloscope via a few resistors to produce a useful display on a VGA monitor. This lets us see what we are sampling as we cant use a real CRO in the digital domain LOL.

Taking some of the learnings from the MAGPI and CCPI circuits I will kick the can down the road and see where it leads.

moodz

[moodz]

Sample rate now set to 24 bits @ 2.5 MSPS ... 400 nanoseconds per sample.

Importantly have now synchronised the TX to the RX. The demod filter is set to 4.78 Hz but the input bandwidth is 1.25 Mhz. ( 2.5 Mhz for synchronous signals )

Below is the UNIPI sampling its own TX pulse signal compared to the CRO ... interestingly the UNIPI picks up ringing on the transitions which the CRO cant see ( only an 8 bit ADC on the CRO ).

Next step is to add the TX front end and coil.

moodz

[Mdtoday]

Nice work Moodz.
I like the use of the blank pcb
Btw, I’ve been busy loading boards over the last week for both KingJL and yourself so you should see a package via Auspost. Hopefully they will beat the Christmas rush.

cheers

[PICON]

Hi Moodz,

I have the same AD7760 Eval board as you, but I could not get true 24bit at 2.5Msps out of it. The least significant nibble would only ever produce the numbers 0,1,8 and 9. Running at 1.25Msps it would give true 24bit. I did check the data on the AD7760 parallel interface with a high speed Logic analyzer but it showed the same missing bits.

I would be interested to see if your AD7760 does the same.

Jeff

[Carl-NC]

interestingly the UNIPI picks up ringing on the transitions which the CRO cant see

Those look like Fourier artifacts. I suspect they are not real.

[moodz]

Nice work Moodz.
I like the use of the blank pcb
Btw, I’ve been busy loading boards over the last week for both KingJL and yourself so you should see a package via Auspost. Hopefully they will beat the Christmas rush.

cheers

ground plane :-) thanks will keep an eye out.

[moodz]

Hi Moodz,

I have the same AD7760 Eval board as you, but I could not get true 24bit at 2.5Msps out of it. The least significant nibble would only ever produce the numbers 0,1,8 and 9. Running at 1.25Msps it would give true 24bit. I did check the data on the AD7760 parallel interface with a high speed Logic analyzer but it showed the same missing bits.

I would be interested to see if your AD7760 does the same.

Jeff

You could be right ... I have not dragged a logic probe across it but the spec sheet says it has 100db SNR at 2.5 MSPS ... which equates to just over 16 bits ? of real resolution at that sample speed so the lower 8 bits could well be noise bits>.

If I get a chance I will tweak the VHDL to look into this issue.

Also from what I understand to achieve best performance at 2.5 MSPS the low power mode must not be set.

[moodz]

Those look like Fourier artifacts. I suspect they are not real.

The internal sampler in the AD77760 is a 40 MSPS analogue modulator followed by a digital filter section ... the ringing could be coming from the filter.

The ring waveform is static though .. it does not move around . ( which is good ).