FPGA based UNIPI system

[moodz]

I added the CCPI front end ... its running off 3.3 volts with around 1.5 amps peak to peak bipolar pulsing. Peak fly back is +/- 200 volts at the coil which is a large Double D.
The RX coil feeds into the ADC ... no gain is applied. The cycle is 512 us.
The red waveform is the sampled signal from the FPGA / ADC.

The yellow waveform is the coil current ( +/- 0.75 amp ) with spiking due to crappy cro probes and flybacks leaking in ;-(

[moodz]

You could be right ... I have not dragged a logic probe across it but the spec sheet says it has 100db SNR at 2.5 MSPS ... which equates to just over 16 bits ? of real resolution at that sample speed so the lower 8 bits could well be noise bits>.

If I get a chance I will tweak the VHDL to look into this issue.

Also from what I understand to achieve best performance at 2.5 MSPS the low power mode must not be set.

Hi Jeff,

I became worried about the noisy 8 bits below 16 bits resolution at 2.5 MSPS and I did find an issue ... the second data read pulse to clock in the LSW and LSB was a bit too short and latching in random rubbish. So I fixed that and placed a short circuit across the input to the ADC. I am fairly sure it is working properly with 24 bit samples as I get the result below .... you can see the flybacks from the nearby ( 10 cm ) 200 volt flybacks leaking via faraday coupling to the front end of the ADC.
The ADC samples 24 bits at 2.5 MSPS ... I then sum each sample 1024 times to give a 34 bit signed summmation then shift 5 bits right to give a corrected 29 bit signed value for each sample point. ( 5 bit oversampling improvement 24 + 5 = 29 bits )

The VGA display generated by the FPGA is 800 H x 600 pixels Vertical ... so you can fit say a 512 ( 9 bit ) scaled value for the waveform in the vertical. So we are looking at bits 13 down to 4 out of the 29 bit full value in the picture below .... If there was random noise happening in the low 8 bits then the wave form would not be as it is. .... I might try an experiment to see if I can measure the thermal noise in a resistor ??

[moodz]

I increased the TX pulse rate to 10 Khz bipolar .. the Tx current is now +/- 1 amp.

Below is a comparison of the 24 bit view from the UNIPI vs the actual signal on a CRO ... note that the CRO signal ( input to ADC ) is only about 300 mV peak to peak whereas the ADC can deal with +/- 3.2 volts so there is room for a 10X preamp here.

I can easily see the UNIPI waveform picking up my 10cm foil target at nearly a meter on the UNIPI display .... and the trace is rock solid though I am in a very noisy lab ... so not much of a test but with 28 bit resolution of which 24 bits are definitely useable ... its extremely promising.

[moodz]

...here is what a target response looks like ( large target so you can see how the waveform changes ).

[PICON]

Hi Moodz,

Are you able to look at your 24bit values stored in memory before you do any summation, as in only capture one full TX cycle. Then have a look at the memory data in 24bit hex to see if the lowest digit in each sample displays the values 0 to F. This how I noticed the issue with my AD7760 at 2.5Msps as the samples for one TX cycle displayed a 0 or 1 or 8 or 9 in the lowest digit.

Jeff

[moodz]

H Jeff,

below is a snap of bits 0 - 7 ( ie LSB ) full speed samples coming in and plotted to the "signal viewer" on the UNIPI ... just looks like high frequency wihite noise. ( as I would expect ).
If there were stuck bits there would be banding in the display .... as per the line on the RHS ... its stuck at a single value becuase the viewer only plots the first 512 samples each time.
If your solution worked OK at 1.25 MSPS but not 2.5 MSPS this points to timing issue on reading out the data ... it states in the data sheet that all reads must be complete before the next DRDY pulse from the chip other wise the 2nd read is corrupted
So both reads have to be completed inside of about 350 nanoseconds.

[PICON]

Hi Moodz,

Can you explain what's on the screen and how it represents the 0-7 bits. Is the vertical the samples or bits.

Jeff

[moodz]

Hi Moodz,

Can you explain what's on the screen and how it represents the 0-7 bits. Is the vertical the samples or bits.

Jeff

Its a virtual CRO implemented inside the FPGA for viewing waveforms represented by signed data coming out of the ADC..... where vertical is "voltage" ie 00000001 00000011 00000010 etc and horizontal is sample 1 sample 2 .... sample 512 and then repeat. I use a range of 512 ( 9 bits ) for the vertical resolution normally as the VGA is 800 Hor x 600 Vert and 512 fits OK into this without overflowing ...

The waveform is all busted up at this speed because we are displaying a 2.5 mhz ( samples per second ) in real time on a VGA display that has a hsync of 70 Khz and vertical sync of 60 hz .... which does not make for a good CRO however if you know this information .... the vertical axis is sample amplitude ... if a value was stuck at F you just get a horizontal line ( ie the value does not change ).
I am not sure that AD would get away with selling an ADC that did not produce the full 24 bits at the claimed sample rates ( even if obviously the lowest bits will be noisy )

There is a gotcha in the spec sheet for this ADC ... its not obviously stated but when you read in the second word ... the 8 bit byte you want to complete your 24 bit data word is in bits 15 - 8 of the second 16 bit word ... not in bits 7 - 0 as one might assume ... bits 7-0 are the status byte. If you read the status byte in as data you will just read stuck bits in the LSB as you describe ...
Paul.

[moodz]

PS I tried the display with just 4 bits ( ie bit 3 to 0 ) or the lowest nibble of the 24 bit word coming out of the ADC and its just random values from 0 to F at a 2.5 Mhz rate.

[PICON]

Hi Paul,

Thanks for the explanation of your screen details. The issues with my AD7760 are not timing as I spent many hours checking that all data and control lines were within specified timing parameters. Maybe I have a faulty AD7760 but at $100AU and not recommended for new designs as stated by Analog Devices, I will not be replacing it. At 1.25Msps it should be adequate for my project.

Jeff

[moodz]

... No worries ..this exercise is just an experiment not a design. If it goes anywhere I will be changing out the adc and fpga ... AMD has been quietly killing off the Xilinx products since the acquired it as well.

[moodz]

...the next stage in the code is working. This is where we take the bipolar pulses and demodulate them so that they are unipolar ( in circuit terms we use a demodulating switch to input of diff amp ).
Next we apply digital amplification .... and our word size is now 72 bits.

Effectively we have an extremely high digital gain.

The displays below show target and non target and we are looking at bits 50 to 41 of the 72 bit word on the wave form viewer. If we were using a CPU we would code this in floating point ... but no need in an FPGA as we just keep increasing the bit word length.
The next step will be integration ...

[moodz]

here is a video of the progress here ...

https://youtu.be/mcT_AAeaaiM?si=Cmfx66Rpz1nuzAKe

[Altra]

Hi moodz, it's great to see you revive this project. What is the horizontal time scale on your vga?

Thanks for sharing

[moodz]

Hi moodz, it's great to see you revive this project. What is the horizontal time scale on your vga?

Thanks for sharing

The horizontal time base in for the last pic was 1.6384 milliseconds per value ( but just for the wave form bit ... as we are really looking at a memory buffer here in real time ).
The update rate of the waveform is 610.35 Hz.
The numbers are weird in decimal because all the DSP is done in pure binary .. not decimal.