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ripped out of a switchmode supply .. nothing special though.
Hey I was trying to compile the display code and I am geting multiple define errors ..
for instance in
LCD.h on line 14
then we have later in the same file ... on line 315
The compiler is saying this is a redefinition of Up_cnt and throws a wobbly .... there are many errors of this type ... any clues ?
moodz, KingJL here... that code originated here and I think you have an early version. When I moved the code to STM (originally developed for Microchip in MPLAB) I had to correct those errors. I think I sent the code for the STM library shortly after you and Brian first arranged access to the LCD. If you cannot locate it, I will send it to you again.
moodz, KingJL here... that code originated here and I think you have an early version. When I moved the code to STM (originally developed for Microchip in MPLAB) I had to correct those errors. I think I sent the code for the STM library shortly after you and Brian first arranged access to the LCD. If you cannot locate it, I will send it to you again.
Added a "Insta balance" button to the prototype detector and pressing this will instantly rebalance the detector.
Here is a video that shows the operation where we tape a ferrite to the coil ... balance it out and keep detecting.
Getting ready for a field test this weekend ... working through some small problems like when you change the ground balance rotary encoder the output chimes ( alot ) due to the sensitivity.
Also heres a question .. I disonnected power to the TX and the detector still works fine ( low sensitivity ) but fine. How is this so ? ( could be a trick question ).
I wanted the detector to initialise with ferrite cancellation in place when the detector is first turned on ... ( so the user does not have to do it ).
The phase resolution on the trial FPGA detector unit is 180/1024 = 0.17578125 degrees ... ( it may seem a bit rediculous using so many decimal places ... but have to remember I am using 32 bit whole numbers ... so every digit actually counts).
A rotary encoder takes care of business for adjust the discrim.
Anyway the short story is that ferrite cancels at 1.93 degrees and this is the turn on setting of the detector now.
I wanted the detector to initialise with ferrite cancellation in place when the detector is first turned on ... ( so the user does not have to do it ).
The phase resolution on the trial FPGA detector unit is 180/1024 = 0.17578125 degrees ... ( it may seem a bit rediculous using so many decimal places ... but have to remember I am using 32 bit whole numbers ... so every digit actually counts).
A rotary encoder takes care of business for adjust the discrim.
Anyway the short story is that ferrite cancels at 1.93 degrees and this is the turn on setting of the detector now.
doh that was before I synchronised the pulse generator at startup ...its really 7.38 degrees ....hmm.
Checking with AD on the availability of the AD7760 ... it seems it was previously not recommended for new designs but that status has changed recently ( last few weeks ) to full production as I believe it is used in certain military designs that cant do without it LOL and they are using lots of them.
So now at the point of ( subject to field testing ) finding / desiging a FPGA or CPU or FPGA CPU combo board which can do the detector engine ( fpga part ) and will bolt straight onto the AD7760 ( even the eval board is good value and saves a ton of effort ) as there is now a truly universal detector platform where you can have PI, VLF, IB or mixture by switching code in the "engine" and making very minor changes in the TX/RX module which could be relays or switches or electronic switches ( which only deals with the waveforms and input protection ) The frontend TXRX module can be the same for any detector mode. The wideband ADC can capture any waveform for demodulation and all the software building blocks are in the FPGA ( mixers / oscillators / demodulators / integrators / correlators / clocks / uarts / spi / etc etc ... you just have to connect the data paths together to change stuff. The internal VGA display generator in the FPGA lets you "see" any waveform and any number can be displayed on the screen also. The only time I used a CRO was to look at the TX waveform on the coil. This has been so handy for development it has saved months of debugging time as you can literally see the errrors in the waveforms. As a user tool you can dial up the sampled voltage right off the coil so you can see if your coil is even working or overloading or you want to see the noise coming in ( like from LED lights etc ).
This is why you dont need amplifier at the front end of the direct sampling ADC metal detector.
My design is sitting at 28 bits resolution at the output ( and I still have maybe 1 or 2 bits of headroom with tweaking ) so the noise is running at +/- 3 bits ( noise from the coil not the ADC ) so I am looking at the 6 nV resolution range with maybe worst case 48 nV of noise. What amplifier can I bolt on there that would make a meaningful difference without upsetting the noise floor ? ANS = practically none. and thats why you dont need one ... if you run out of gain keep lifting the bit count and I reckon I could reach 32 bits with extreme tweaking.
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