uPC Controlled PI

[KingJL]

Is Mr King still here?

Occasianally

[der_fisherman]

Hi Mr King,

is this (great) project now "shelved"?

regards

Andy
PS. Your work made really great reading, thanks for that.

[KingJL]

Hi Mr King,

is this (great) project now "shelved"?

Yes. I felt like we/I was re-inventing the same wheel. I did learn a world of information with the effort. I decided to re-visit the Goldscan IV, not to re-invent it, but with the goal to really understand it. I think I have succeeded in that. My past endeavors and my experience with embedded systems has convinced me that no real progress will be made using inexpensive general purpose uPC's. Real progress will require very fast specialized DSP processors or FPGA's (actually my preferred approach). Either way, power requirements significantly increase and require more robust power solutions to provide 'in-the-field' operatioanl time. Although with the DSP/FPGA, the +- 5v analog supply requirements can be significantly reduced, by only using the pre-amp section to shift the RX to the level for the ADC. So, until I get ambitious enough to tackle the FPGA, my development activities are at rest as I have found that co-operative efforts really don't seem to work.

I do think that a "Goldscan IV" implemented digitally in an FPGA would be awesome.

[der_fisherman]

Yes. I felt like we/I was re-inventing the same wheel. I did learn a world of information with the effort. I decided to re-visit the Goldscan IV, not to re-invent it, but with the goal to really understand it. I think I have succeeded in that. My past endeavors and my experience with embedded systems has convinced me that no real progress will be made using inexpensive general purpose uPC's. Real progress will require very fast specialized DSP processors or FPGA's (actually my preferred approach). Either way, power requirements significantly increase and require more robust power solutions to provide 'in-the-field' operatioanl time. Although with the DSP/FPGA, the +- 5v analog supply requirements can be significantly reduced, by only using the pre-amp section to shift the RX to the level for the ADC. So, until I get ambitious enough to tackle the FPGA, my development activities are at rest as I have found that co-operative efforts really don't seem to work.

I do think that a "Goldscan IV" implemented digitally in an FPGA would be awesome.

Dear Mr King,

great reply and I am sure that there is a lot of truth in what you say, but it might be sad for anyone who was building a "KingFisher"......but still your right to stop......

By the way, have you ever thought of building in several (cheap?) processors, each one "tuned" to do a specific task or tasks, to spread the load around? That is a common method in the computing industry.

Your FPGA idea is of course the absolute best for speed, power saving and flexibility and there is plenty of good developement software around, some free I am told....though I am personally totally ignorant of the way to design such a chip......

Best wishes in whatever you do and do keep us involved.

regards

Andy

[6666]

Sorry to hear your project is dead
did you ever do any codes for the older 16f84a chips
for just the timing pulse and the 2 samples ?

[moodz]

Does anyone have scopeshots of GS4 timing pulses and I will compile a chip to do it.
Moodz

[mohandes]

can use this project on all PI machine like barracuda , Dp ,....

[Orbit]

Hello Moodz, I have I can send you send me a private message with your email !

[6666]

Orbit I have sent you a PM
6666