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Originally posted by Carl-NC
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300 ns advantage (what you get from the diode trick) doesn't make a difference if the amplifier cuts off at 200kHz. -
As Carl said, the theory seems to make sense, which is why I decided to investigate further.
From simulation it is clear that the MOSFET output capacitance appears to get disconnected from the coil by the diode. You can see that by examining the shape of the coil current after TX-off. There is a small hump in the decay curve where the coil's parasitic capacitance initially becomes charged and then subsequently discharges. This hump is reduced in amplitude when the diode is present. Also, the amount of reduction is related to the ratio between the MOSFET's output capacitance and the coil's parasitic capacitance.
But ... in practice (on a real circuit) the opposite appears to be true.
I currently need to rebuild my test circuit, so it might be some time before I can do some in-depth testing.
Please keep up this interesting discussion.Comment
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The thought was to use a diode to allow earlier sampling. Maybe we should define the desired delay. I've been using the diode to allow sampling starting at 6usec. Is 6usec low enough? The chart I included in reply #4 showed a big gain in distance for the 4grain nugget. The nuggets were tested with the flat side towards the coil. The difference in detection distance would be greater for the 4grain and 10grain nugget if turned on edge. Coins were better at 6usec but not a lot better. Might be a lot better with coins turned on edge? If we can start target sample at desired delay with better S/N without the diode all the better. Including chart from reply#4. Different coil or circuit might show different.Comment
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I've run a simulation using the MOSFET model below (IRFIBF30G, 900V, 2A) and there was no difference whatsoever between diode or no diode. But then again it seems the model's capacitances are too low? (CGS 54.8p, CGD 69.5p).
According to the data sheet the output capacitance at 25V is 320pF. However, the total gate-drain charge at 360V is 42nC, equivalent to 116pF (42nc/360V). I wonder if there's anything in the model below that adjusts the capacitances according to the voltage, caus I can't spot it.
When I use the defautl LTSpice model
.model IRFIBF30G VDMOS(Rg=3 Rd=5m Rs=1m Vto=3 Lambda=0.0031 Kp=1.7 Cgdmax=1.5n Cgdmin=150p Cgs=1.2n Cjo=320p Is=2.3p Rb=6m mfg=Vishay Vds=900 Ron=3.7 Qg=78n)
I do get a clear difference in timing.
What gives?
Code:*IRFIBF30G MCE 12/11/97 *Ref: International Rectifier Product Digest '94 *900V 2A .632ohm Power MOSFET pkg:TO-220 2,3,1 *SYM=POWMOSN .SUBCKT IRFIBF30G 10 20 40 40 * TERMINALS: D G S M1 1 2 3 3 DMOS L=1U W=1U RD 10 1 0.299 RS 40 3 16.8M RG 20 2 787 CGS 2 3 54.8P EGD 12 0 2 1 1 VFB 14 0 0 FFB 2 1 VFB 1 CGD 13 14 69.5P R1 13 0 1 D1 12 13 DLIM DDG 15 14 DCGD R2 12 15 1 D2 15 0 DLIM DSD 3 10 DSUB LS 30 40 7.5N .MODEL DMOS NMOS (LEVEL=1 LAMBDA=2M VTO=3.1 KP=0.426) .MODEL DCGD D (CJO=69.5P VJ=0.6 M=0.68) .MODEL DSUB D (IS=7.89N N=1.5 RS=0.421 BV=900 CJO=106P VJ=0.8 M=0.42 TT=171N) .MODEL DLIM D (IS=100U) .ENDS
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Figure 5 in the datasheet shows how Coss varies with VDS, but it looks like the MOSFET subcircuit has fixed values for CGS and CGD. Note that NMOS is a basic first generation level 1 (Shichman and Hodges) model, so I don't think Coss variation with VDS is included. In fact, I seem to remember that level 1 models do not handle the charge correctly.Originally posted by Teleno View Post
Have a look at this -> https://class.ee.washington.edu/cadt...chapter_16.pdf
I suspect you'll need a much higher level model (BSIM?) to get correct results.Comment
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I have drawn the SPICE model of the IRFIBF30G and it seems that it is actually modelling the non-linear capacitances using current/voltage ources and Miller effects:Originally posted by Qiaozhi View Post
The result of a simulation diode/no_diode when the damping resistors are adjusted to get the same overshoot, is as follows:
This was for a larger MOSFET IRFP450LC with more capacitance using similar non-linear model.
Code:********** *IRFP450LC MCE 12/12/97 *Ref: International Rectifier Product Digest '94 *500V 16A .075ohm Power MOSFET pkg:TO-247 2,3,1 *SYM=POWMOSN .SUBCKT IRFP450LC 10 20 40 40 * TERMINALS: D G S M1 1 2 3 3 DMOS L=1U W=1U RD 10 1 34.6M RS 40 3 2.88M RG 20 2 49.4 CGS 2 3 461P EGD 12 0 2 1 1 VFB 14 0 0 FFB 2 1 VFB 1 CGD 13 14 585P R1 13 0 1 D1 12 13 DLIM DDG 15 14 DCGD R2 12 15 1 D2 15 0 DLIM DSD 3 10 DSUB LS 30 40 7.5N .MODEL DMOS NMOS (LEVEL=3 VMAX=1.04MEG THETA=58.1M ETA=2M VTO=3.1 KP=4.42) .MODEL DCGD D (CJO=585P VJ=0.6 M=0.68) .MODEL DSUB D (IS=66.4N N=1.5 RS=37.5M BV=500 IBV=2M CJO=893P VJ=0.8 M=0.42 TT=324N) .MODEL DLIM D (IS=100U) .ENDS
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Yes. I use about 1 amp peak coil current. The time spent at avalanche is short, less than 1/2usec. with the diode. Less if it does avalanche with no diode. I used a IRF740 when first comparing diode no diode on the bench. Tried a STP11NK40 yesterday with no diode. Amplifier came out of saturation at around 7usec instead of about 10usec. Including a spice analysis, diode no diode with 1 amp peak current. Don't know how to enter a IRF740 or STP11NK40. Amplifier gain, 300 to 450. The coil volts has to decay to around 5mv before the amp can come out of saturation. I am using a IB coil now. Still have a diode in the Tx circuit. Sampling at 6usec. I will try no diode to see if it effects an IB coil. I've been using the diode because it's the only way I've found to sample near 5usec.Originally posted by Qiaozhi View Post
Need to start with a circuit resonance around 1MHz(amplifier and Rd disconnected) for the diode to make a difference?
D2 added to clamp the fet(avalanche volts)Comment
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There's definitely some sort of modelling going on there using controlled sources, and your back-engineered schematic is correct ... except that RS should be connected between nodes 3 and 40, whereas you have it connected between 3 and 30. Actually, there appears to be a mistake in the subcircuit, as the inductor LS is connected to node 30, which doesn't exist anywhere else. Basically, it's floating. Your interpretation may in fact be the correct one.Originally posted by Teleno View PostComment
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Hi TelenoOriginally posted by Teleno View PostI have drawn the SPICE model of the IRFIBF30G and it seems that it is actually modelling the non-linear capacitances using current/voltage ources and Miller effects:
The result of a simulation diode/no_diode when the damping resistors are adjusted to get the same overshoot, is as follows:
This was for a larger MOSFET IRFP450LC with more capacitance using similar non-linear model.
Code:********** *IRFP450LC MCE 12/12/97 *Ref: International Rectifier Product Digest '94 *500V 16A .075ohm Power MOSFET pkg:TO-247 2,3,1 *SYM=POWMOSN .SUBCKT IRFP450LC 10 20 40 40 * TERMINALS: D G S M1 1 2 3 3 DMOS L=1U W=1U RD 10 1 34.6M RS 40 3 2.88M RG 20 2 49.4 CGS 2 3 461P EGD 12 0 2 1 1 VFB 14 0 0 FFB 2 1 VFB 1 CGD 13 14 585P R1 13 0 1 D1 12 13 DLIM DDG 15 14 DCGD R2 12 15 1 D2 15 0 DLIM DSD 3 10 DSUB LS 30 40 7.5N .MODEL DMOS NMOS (LEVEL=3 VMAX=1.04MEG THETA=58.1M ETA=2M VTO=3.1 KP=4.42) .MODEL DCGD D (CJO=585P VJ=0.6 M=0.68) .MODEL DSUB D (IS=66.4N N=1.5 RS=37.5M BV=500 IBV=2M CJO=893P VJ=0.8 M=0.42 TT=324N) .MODEL DLIM D (IS=100U) .ENDS
We are interested in coil volts less than 10mv. Would be a lot easier to see if you made +volts ground.Comment
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Looking at Teleno's circuit, coil resonance around 640kHz. I've been using around 1MHz. The higher the coil resonance the greater the potential gain using the diode. Not saying what we should be using but can we agree on a resonance value. I have made a few 300uH coils with 30 inches of twisted pair for lead with a resonance round 1MHz. Not hard to make coil resonance higher but adding the lead usually brings it down to around 1MHz.Comment
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Relax, it's not an actual project, just a simulation to verify the point of using a diode.Originally posted by green View Post
The coil's L and R values are from a Minelab's GPX coil that I own. C is just an educated guess.
By the way, what do you mean by "twisted pair for lead"? do you have a pic or a diagram?Comment
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It appears that the MOSFET subcircuits posted by Teleno are modelling the nonlinear variation of Coss as a function of drain to source voltage Vds. The value quoted in the datasheet is specified at 25V, which is not that useful for our purposes. It is more useful to know the value of Coss effective, which is defined as a fixed capacitance that would give the same charging time as the output capacitance of a MOSFET while Vds is rising from zero to 80% Vds with Vgs = 0V.
The attached simulation shows two test circuits (one for each of the MOSFETs). If you measure at the 80% point (480V for top circuit, and 600V for bottom circuit) the Tc is 27.9us and 16.6us respectively.
Then, using:
we have:for the top circuit,
and:for the bottom circuit.
Note that the voltage sources are set to the maximum voltage for each MOSFET. If you raise these voltage to 600V and 1000V, you can readily see that the avalanche voltage is also modelled correctly.
Green - this may also answer your question about how to attach third-party subcircuits. You can also use the .lib directive to point to a file.Comment
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Very educational, thanks!Originally posted by Qiaozhi View Post
The (theoretical) conclusion is that the diode would be useful/noticeable when the value of Coss is near the coil's capacitance or larger, which is not the case for quick and dirty home-made coils above 300uH with capacitance in the order of 200-300pF.
Regarding third party libraries, this is the one I used is mcemos.lib (attached). Copy the .lib file to the /sub directory and the .asy file to the /sym directory. You'll get a new symbol called "MCEMOS", usit by changin the name to the mosfet of interest in the library.Comment
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Including a picture of twisted pair stranded I purchased(pvc coated, each wire about 1.38mm OD, measures about 1.3pf/inch). Purchased some AWG24 stranded hookup wire, pvc coated, about 2.1mmOD). Cut a piece about 65 inches long, wrap around a small fixed dowel, evened ends and wrapped, taped both ends, cut end around dowel. Measures about .9pf/inch.Originally posted by Teleno View Post
Changed the amplifier and integrator circuit in my detector last week. Used some 25x25mm aluminum foil targets(1,2,3,4 and 5 layers) Carl suggested in another thread to compare signal loss for short TC targets at 6, 10 and 14usec delay times. Included 4 and 10 grain nugget to compare with prior test. Coil stationary, target swinging from a pendulum, threshold adjusted for a minimum of 10 sec. between noise flashes, target lowered until led flashed a least 5 target crossing in a row.
Target sample time was about 10usec for all of todays tests.Comment
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