Minipulse JFet explanation needed.

[Brian Deese]

I have the minipulse plus assembled and I am scoping everything to verify before I connect a coil,and the connection to the preamp. On TP7,and TP8 I have the sample pulses going to the JFets, the pulses go from -5V to 0V the question I have is how are we turning on a JFet with a Positive going pulse? I have no experience with JFets I am sure I am not understanding the way this circuit works.

[dbanner]

N-channel JFET negative 5 volts on gate, the FET is switched off, and for the duration of the sample at 0V on the gate, the FET is switched on.

I found a PDF document on another mini-pulse thread with scope shots of all the test points. Maybe you have it already.

[Brian Deese]

I think I must need a multi vitamin,or more turkey sandwiches. My brain wants to clock out at 5pm. Thanks for the pdf I'll check it out tomorrow on the desktop.

[dbanner]

A quick read up on n-channel jfet indicates that a negative voltage on the gate is required for "pinch off" to occur. This is the voltage at which the source to drain stops conducting.
At zero gate voltage, the source to drain is fully conducting.
Now it's easy to see the action of the N-JFET as a sample switch with the pulse train provided by the 4538's

[Brian Deese]

Pretty obvious isn't it, my oversight. Have you built one of these? I have a small offset in the preamp output that I'm not crazy about. If I jumper the rx connection which grounds the input I get about -800 mv on the output.

[6666]

With the MPP you dont have to worry about the pre amp off set as its capacitor coupled, I hate Jfets to

[dbanner]

A quick read up on n-channel jfet indicates that a negative voltage on the gate is required for "pinch off" to occur. This is the voltage at which the source to drain stops conducting.
At zero gate voltage, the source to drain is fully conducting.
Now it's easy to see the action of the N-JFET as a sample switch with the pulse train provided by the 4538's

About the pulse train provided by the 4538's, it pulses between -5v and 0 volts. This is because Vdd(pin16) is at 0 volts and Vss is at -5V.

[surfdetector]

A quick read up on n-channel jfet indicates that a negative voltage on the gate is required for "pinch off" to occur. This is the voltage at which the source to drain stops conducting.
At zero gate voltage, the source to drain is fully conducting.
Now it's easy to see the action of the N-JFET as a sample switch with the pulse train provided by the 4538's

Thanks for that. You presented a very clear explanation.
Cheers

[dbanner]

There is a difference between Vgs cut off voltage and "pinch off" I think. But more in depth study is required to fully appreciate the characteristics of this ubiquitous voltage controlled device.

[Carl-NC]

The Vgs cutoff voltage is the same as the Vp rating. Transition from linear to saturation occurs at Vgs-Vp. Vp is determined when Vgs=0, and when Vgs=Vp there is no Ids regardless of Vds.

There is an inherent risk in using a JFET for a demod switch. If the source is connected to a fixed voltage (say, virtual ground in an inverting opamp integrator) then the Vgs control will be consistent regardless of the input signal on the drain. But if the JFET source voltage varies with signal level as it does with a differential integrator then Vgs will also vary with signal level, and so will the channel resistance. It may not be a Big Deal in a PI design, and might even be a benefit as the integrator gain will tend to decrease for large signals. It's something to consider, especially if you see weird behavior with large signals.

[waltr]

Excellent description of using a JFET for a switch.

The down side mentioned is a reason to use an analog switch chip like a 4066. Internal circuits negate these issues.

[Carl-NC]

The down side mentioned is a reason to use an analog switch chip like a 4066. Internal circuits negate these issues.

The 4066 has parallel N & P channel devices, so as the voltage level changes one of them is always low-impedance.

[dbanner]

Aha, The 4066 chip always is a big headache to route the tracks on a pcb. Especially if utilizing all four switches. A nightmare for the hobby man.

[waltr]

Aha, The 4066 chip always is a big headache to route the tracks on a pcb. Especially if utilizing all four switches. A nightmare for the hobby man.

Yes, it is. That is why I used JFETs when I built the Hammer Head.

There are many newer, better analog switches available in quad, dual and even singles. However, most if not all are surface mount only.
For a PI with a differential integrator Duals would work in the layout.

[surfdetector]

N-channel JFET negative 5 volts on gate, the FET is switched off, and for the duration of the sample at 0V on the gate, the FET is switched on.

I found a PDF document on another mini-pulse thread with scope shots of all the test points. Maybe you have it already.

I have done videos of all of the steps for the MPP Rev E which might be of more help for those doing the latest boards.
https://www.youtube.com/playlist?lis...x32pI5m-di2GTf