Preamp

[Chet]

Hi Teleno
I like the way you set up the -5v regulator for the ATtiny84 and the ADC. I lack the knowledge to understand all of the workings of the receiver circuits. Maybe later when get your final design you could give us less talented a simplified explanation?
Thank you,
Chet

[Teleno]

Teleno, I agree. As long as the design can be reproduced AND we can keep the digital noise form the MCU out of the works it is a better and more flexible way to go.
I was mainly concerned about the desires of others:<)
The question then is you going to willing to either provide either preprogrammed MCU's OR to share the code, and instructions on how to program it?

I'm willing to write the code with all of you, perhaps set up a separate thread for that. But for now I'm concentrating on the amplifier alone.

Hi Teleno
I like the way you set up the -5v regulator for the ATtiny84 and the ADC. I lack the knowledge to understand all of the workings of the receiver circuits. Maybe later when get your final design you could give us less talented a simplified explanation?
Thank you,
Chet

Q2 is set up as a very low impedance, common-base amplifier. p-FET J4 maintains the collector of Q2 a fixed, controlled voltage relative to Vdd. Together they form a cascode configuration. Because there's no voltage swing at the collector of Q2, its output capacitance has no effect on the bandwidth. Instead, it's the output capacitance of J4 (which much lower - 2pF) and R2 what limits the speed of the response.

n-FET J1 is a constant current sink. It fixes the base voltage of Q2 at a steady value relative to Vdd.

Together with p-FET J4 it has the effect of attenuating any spurious variation of Vdd. With the values shown the attenuation is 52dB, or 1/400. For example, a 100mV ripple is translated into 250uV at the preamp's output.

Temperature compensation of Q2 is provided by D3.

The gain of the stage is a little under R2/R1, where R1 is the damping resistor.

The collector current in Q2 should be chosen for the smallest Noise Figure usually specified for 100uA - 200uA for small signal transistors. Q2 could better be BC559 (low noise version of BC557).

[Old cart]

teleno, can you control when the ADC samples accurately. Also the model I looked at had only a 10 bit 16 kS/S ADC. Theat may not be fast enough.

[Teleno]

teleno, can you control when the ADC samples accurately. Also the model I looked at had only a 10 bit 16 kS/S ADC. Theat may not be fast enough.

I'll be taking 2 samples per cycle of 1ms, an early sample at 5us and a late sample (EF) just before the Tx pulse. For this it is fast enough.

10 bit at 5V provides a resolution of 1.2 mV which is OK because the noise output level will be about 2mV with 700 gain.

Control of sampling time can be made accurate to one clock cycle (62ns at 16MHz) as follows:

- Write Tx-on pulse to port,
- start Timer,
- enable Timer interrupt.

When the timer interrupts:

- write Tx-off to port,
- start counting loop (set your delay here),
- sample ADC
- wait till conversion is ready.

[Chet]

Teleno
Wow!
That is quite involved and ingenious.
Thank you for the explanation and quick reply,
Chet

[Teleno]

Teleno
Wow!
That is quite involved and ingenious.
Thank you for the explanation and quick reply,
Chet

Hey, no problem! Electronics is my passion.

More explanations:

- D2 prevents the reverse Vbe voltage to go beyond -0.7 V. Higher values can degrade the transistor mddle term, values above -5V will pemanently damage it.
- R15/D1 limit the current in Q2 during flyback to 20mA.
- After flyback, D1 is closed and the coil current (target current) flows through Q2 and J4 into R2, causing direct amplification.

[Old cart]

I'll be taking 2 samples per cycle of 1ms, an early sample at 5us and a late sample (EF) just before the Tx pulse. For this it is fast enough.

10 bit at 5V provides a resolution of 1.2 mV which is OK because the noise output level will be about 2mV with 700 gain.

Control of sampling time can be made accurate to one clock cycle (62ns at 16MHz) as follows:

- Write Tx-on pulse to port,
- start Timer,
- enable Timer interrupt.

When the timer interrupts:

- write Tx-off to port,
- start counting loop (set your delay here),
- sample ADC
- wait till conversion is ready.

If you only take one sample will there not be a lot of noise? Typically sample windows represent maybe 10Us of integrated data. A single sample would not have this advantage unless you average many of the samples, one target taken after each transmit pulse, together to form the equivalent integration effect. I do not know how to calculate how many samples would have to be averaged to get equivalent noise reduction.

[Teleno]

If you only take one sample will there not be a lot of noise? Typically sample windows represent maybe 10Us of integrated data. A single sample would not have this advantage unless you average many of the samples, one target taken after each transmit pulse, together.
to form the equivalent integration effect. I do not know how to calculate how many samples would have to be averaged to get equivant noise reduction.

I have designed for speed as a means to improve the Signal/Noise ratio, for early samples increase the amplitude exponentially (the best noise filter). Surfmaster, for example, waits 15us before acquiring a sample and no amout of integration will recover the signal decayed in the delay.

We'll see how it pans out.

[Sean_Goddard]

Point taken on mixing threads.

The micro will have some fancy filtering afound it and careful ground plane placement. Can I suggest you design with an Analogue ground and a Digital ground then I can star the analogue ground an bring the main feed back to the battery connection point.

[Teleno]

Point taken on mixing threads.

The micro will have some fancy filtering afound it and careful ground plane placement. Can I suggest you design with an Analogue ground and a Digital ground then I can star the analogue ground an bring the main feed back to the battery connection point.

The digital and analogue grounds have to be the same because the ADC input of the MCU must be referenced to the same ground as the amplified signal. This ground is the OUT terminal of the LM79L05.

I will publish a more detailed schematic later.

[Teleno]

I would welcome suggestions on how to interface the amplifier with the MCU's ADC.

For a 12V supply:

- The preamp's output is 6V - 7V and is passed on to the OpAmp non-inverting input.

- The OpAmp's output can swing between 3.8V - 8.2V = 4.4V (AD8610) and passed on to the ADC of the MCU.

- The MCU is powered at 5V.

So the problem is to adapt the 3.8V - 8.2V of to OpAmp to the 0V - 5V of the MCU.

One solution is to create a floating digital ground at about 7V for the MCU. But then the maximum swing at the ADC input would be 7V - 8.2V = 1.2V instead of the 5V that could be achieved.

Another solution is a a floating digital ground at 3V and a regulated rail at 8V. Then the OpAmp's output can cover most of the ADC input range.

Finally, a rail-to-rail JFET OpAmp can be used that's as least as fast as the AD8610 (List here). Then a simple LM78L05 regulator would power the MCU.

(P.S. AD8065 for $5 looks good- 7nV noise. AD8033 is $5 but 11nV noise. AD8067 is $6 with 6.6nV noise and 640uV/s slew rate. All in SMD packages only).

As a last resort the OpAmp can be scrapped and a discrete second stage be used (see my first version of the amplifier) in which case we're also served with an LM7805.

[Qiaozhi]

I would welcome suggestions on how to interface the amplifier with the MCU's ADC.

One method I've used successfully in the past (where the opamp output swings between +/-5V) is to split the opamp output into two channels, where each channel is a precision rectifier. https://en.wikipedia.org/wiki/Precision_rectifier
One channel allows the positive part of the signal through, and the second channel passes the negative portion. If you make the negative channel inverting, you now have two signals which go from 0V to +5V. Feed these signals into two separate ADC inputs on the PIC. Then it's a simple task to combine these two inputs in software.

[ODM]

It's a novel design, but for the following effects I can't agree that this amplifier will behave indepently of noise riding on battery voltage.
* The ADC is tied to a fixed reference based on the logic voltage ground.
* Supply noise on the negative rail will affect the constant current drives.
* The JFET input amplifier is referenced to -Vbatt*(5/7), and this is multiplied by a gain of feedback resistor and equivalent of voltage divider, which means the PSRR is -24dB! I suggest coupling this stage with a decent capacitor to the reference of the previous stage, preferably no ceramics or failing that a good quality NP0 since it's a signal carrying cap.

Battery voltage will display a slow recovery after brief current pulses like PI transmit. Fortunately it can be constant enough not to show up in actual performance but driving a loudspeaker or headset can couple to the detector via battery voltage through this insidious means.

Can you run an AC analysis on your circuit with the reference signal riding on battery voltage, and a time domain analysis with a 10ns risetime squarewave riding on battery voltage? These are usually good tests for suggesting where attention to supply is needed.

Combining the coil damping and amplifier input resistor is an interesting thing, something I played with on a fisher impulse like recycling design, helping avoid the input guard diodes slowing flyback. The problem is that with fast coils the optimal damping resistor value rises and makes for a higher input resistor than you'd want.

[Teleno]

It's a novel design, but for the following effects I can't agree that this amplifier will behave indepently of noise riding on battery voltage.
* The ADC is tied to a fixed reference based on the logic voltage ground.
* Supply noise on the negative rail will affect the constant current drives.
* The JFET input amplifier is referenced to -Vbatt*(5/7), and this is multiplied by a gain of feedback resistor and equivalent of voltage divider, which means the PSRR is -24dB! I suggest coupling this stage with a decent capacitor to the reference of the previous stage, preferably no ceramics or failing that a good quality NP0 since it's a signal carrying cap.

Thanks for your input, good to meet someone who understands circuit design.

You're right, the digital ground and the OpAmp input are not referenced to -Vbatt while the signal at R2 is.

To remedy these issues the voltage divider is scrapped and I'm using a current source on R11. This the Thevenin equivalent of a steady voltage source in series with R11. It determines the baseline of the output vout.

The digital ground referenced to +Vbatt is also scrapped, this new version uses -Vbatt as the common ground to all circuits.

The role of the JFET OpAmp in the new design is no longer to provide a gain block, but buffering (gain close to 1) and voltage-to-current conversion. This lowers the speed requirements for the OpAmp since extremely high slew rates are no longer necessary. Common ICs such as TL071 or LF357 can be used with little or no speed penalty compared to AD8610.

Gain is achieved by a current mirror at the OpAmp output which also provides referencing to -Vbatt to isolate the output from power ripples.





AC analysis of a reference signal Vn1 riding on battery voltage:






The premp stage has a PSRR of -52 dB, but then the second stage amplifies everything it gets by the ratio R5/R11 and the PSRR at the output is just -28 dB.

Combining the coil damping and amplifier input resistor is an interesting thing, something I played with on a fisher impulse like recycling design, helping avoid the input guard diodes slowing flyback. The problem is that with fast coils the optimal damping resistor value rises and makes for a higher input resistor than you'd want.

The next modification would be to apply Moody's variable damping circuit so that the input resistor is high during most of the transient but then drops to about 500 ohms at the end. This has the benefits of faster decay (larger S/N ration) and lower noise and the drawback of a sensitive adjustment that would have to be performed by the MCU.

The output seen by the ADC sampler should look like this:

[Teleno]

I think current sourced/sinks J1/R13 ahd J2/R14 should be replaced by shunt bandgap references (LM337/LM317) to achieve maximum ripple rejection. Other ideas?