Preamp

[Teleno]

I think current sourced/sinks J1/R13 ahd J2/R14 should be replaced by shunt bandgap references (LM337/LM317) to achieve maximum ripple rejection. Other ideas?

The answer is no, the LM337/LM317 are not fast enough and slow the samoling down by 4usec.

The current sources/sinks have to be fast, so RF JFETs are the only option.

[Old cart]

The answer is no, the LM337/LM317 are not fast enough and slow the samoling down by 4usec.

The current sources/sinks have to be fast, so RF JFETs are the only option.

Did you answer your own question?

[Teleno]

Bad news, OpAmp (LT)Spice models are generally not suitable for PSRR simulations (Power Supply Rejection Ratio). The results and the characteristics in the datasheets do not match by a large margin. Actually LTPsice grossly underestimates the PSRR.

[Davor]

The most Spice models simplify opamps by means of modelling only the input circuitry, and the rest is just a piecewise linear "gain block". In most cases it is OK, as such models run much faster than the full model with all transistors accounted for. Bur as you say, there are cases it is not good enough.

[ODM]

Reading the documentation on their opamp simulation models is a good starting point. In the earlier case I presented, the opamp's own PSRR that would be around 40-80dB would largely be swamped by the circuit's own supply rejection ratio that was up to 60-100dB worse (yes, that means supply variations actually show up in output with gain instead of attenuation).

It's important to do these simulations as straight up AC simulations, injecting the stimulation individually to each path (ac voltage in series with path) to see what individual paths have the largest effect on the overall output. Don't use a noise simulation for measuring response for individual distubance sources. Noise simulation is useful but it is very easy to interpret wrong.

To simulate an opamp's PSRR you need the complete simulation model for that opamp, some manufacturers do supply their simulation models which is nice. It's easy to check whether they match the presented PSRR spec with the AC simulation's AC voltage injected into the supply. If the simulation model does not have PSRR support it is hardly LTSpice's fault, luckily adding simulation parameter listings is easy

[Teleno]

This version uses improved current sources for better PSRR at the two biasing nodes (Q2/D3 and R11/R12).

The output can swing between 270mV and 5V.
Gain: 480
PSRR: -64 dB
Sampling delay: 6 usec.
Input referred noise level: 2.5 uV
Output noise level: 1 mV



Power Supply Rejection Ratio:

[ODM]

Looks nice with a reasonable number of parts for a discrete frontend. When you prototype this one I recommend building it on plain copper board. How fast is your 'scope, analog/digital?

The only caveat I see on a quick glance is that there's no reference from the coil's cold end (VDD) after the first amp stage. Usually translating a signal from a reference to another is done by an instrumentation amplifier kind of circuit that takes a signal and a reference, and translates it to another signal with a separate reference.

This is just a gut feeling but I imagine your PSRR stems mostly from having amplifiers referenced via current source and resistor combinations to both ends of the battery without a common signal ground.

[Teleno]

The only caveat I see on a quick glance is that there's no reference from the coil's cold end (VDD) after the first amp stage. Usually translating a signal from a reference to another is done by an instrumentation amplifier kind of circuit that takes a signal and a reference, and translates it to another signal with a separate reference.

The cold end is referenced via R1 and R6 to the "virtual ground" of Q2's emitter. This is a common base configuration with gain aaprox. R2/R1.

This is just a gut feeling but I imagine your PSRR stems mostly from having amplifiers referenced via current source and resistor combinations to both ends of the battery without a common signal ground.

Certainly there's no common signal ground, but the PSRR is necessary whenever a fixed reference is required expecially if that reference is going to be amplified. Although C2 attenuates the supply swings coused by the Tx pulses, the slow recovery means the cap is still charging while the signal is being sampled. This supply ramp needs to be eliminated fro the output.

[ODM]

Sorry, didn't state myself clearly; by cold end I mean the end where voltage swings are pretty small compared to the hot end that swings from battery voltage to flyback peak.

Be careful when touching the ramp, since the wanted signal is riding atop that ramp Most differential frontends use the coil cold end directly as a reference, which rids the signal of any capacitor charge ramp issues - until the reference changes, anyway. These reference changes are always a chance for some surprise pains, thus it's a good idea to reference one's A/D conversion to the same supply as the coil driver is. Microcontroller single ended ADCs can be nasty about it and their supply rejection generally goes down the drain when coupling their reference anywhere except the mcu's ground.

[Teleno]

Be careful when touching the ramp, since the wanted signal is riding atop that ramp

That's why I use the ramp as the reference, to separate the signal from the ramp.

The base of Q2 is referenced to the ramp, J2 with its gate attached directly to the ramp provides a steady collector voltage (rerefenced to the ramp) for Q2. Actually the 1st stage suppresses the ramp by -80 dB (at Vtest) and outputs a signal referenced to GND via a high output impedance cascode Q2/J2.

The second amplifier stage is referenced to GND. The MCU and its ADC are also referenced to GND. The offset bias for the OpAmp is isolated from the ramp by the current source J3/J4 which provides -80 dB suppression.

I believe everything has been though out and the amplifier is ready for breadboarding. Is anyone up to designing the PCB?

[Davor]

Well, I was not much around here lately, so I couldn't interfere before. I fail to see any DC referencing mechanism. Are you going to set the DC bias by means of adjusting the source resistances for the given FETs, or am I missing the point?

It is not critical since EF sample is applied further on, so DC reference may float. But some general range must be set.

Same goes with PSRR obsession. Since you use ADC further on, and you use the very same power supply in a whole design, wouldn't it be more efficient to simply use voltage divider from the PSU as a voltage reference for ADC? High frequency components will only act as a kind of dithering anyway.

[Teleno]

Well, I was not much around here lately, so I couldn't interfere before. I fail to see any DC referencing mechanism. Are you going to set the DC bias by means of adjusting the source resistances for the given FETs, or am I missing the point?

If you look at the top-right corner of the schematic you can see the instructions (in blue) to set the DC working points. They're set by adjusting the source resistances of the JFETS.

1. Adjust R3 to obtain 6V at point "Vtest".
2. Then adjust R5 to obtain the desired baseline at "Vout", something between 200 mV - 500 mV is fine.

U2 can be any fast JFET OpAmp. Rail-to-rail variants are not necessary because the inputs will vary around the mid-point of the power supply (6v) and MOSFET M2 provides the rail-to-rail output by subtracting its own threshold from the OpAmp's output.

Same goes with PSRR obsession. Since you use ADC further on, and you use the very same power supply in a whole design, wouldn't it be more efficient to simply use voltage divider from the PSU as a voltage reference for ADC? High frequency components will only act as a kind of dithering anyway.

Is PSRR is poor, the power supply recovery ramp (that follows the high current Tx pulses) will add different levels to the EF component at the signal sampling point and at the EF sampling point. What's worse, the power component will vary as the battery discharges. This is not good if you want to do Earth Field and Ground Balance. To avoid this I make sure the PSRR is enough to push power fluctuations below the output noise at the very least.

I prefer a good PSRR as it makes the signal a lot more solid. Besides, it's easy to achieve.

The ADC works on a regulated 5V supply. I might look at using this supply (which already has a good PSRR) for biasing instead of the JFETs, but I'm afraid the schematic won't get any simpler than this and then there's the high noise noise of the regulator, a problem the JFETs don't have.

[Davor]

I beg to differ in the part of PSRR influence on EF. Few people understand what EF actually does, but in case you are worried about influence of PSRR on signal sampling arithmetics, you should try the voltage reference trick I mentioned above.

The ADC voltage reference input effectively works as a 1 quadrant divider. It thus normalises binary data.
Say, Vcc rises for 10%, the ADC step is raised also by 10%. If a signal is also risen by 10% due to a Vcc jump, it will be presented with a same binary value after ADC.

[Teleno]

I beg to differ in the part of PSRR influence on EF. Few people understand what EF actually does, but in case you are worried about influence of PSRR on signal sampling arithmetics, you should try the voltage reference trick I mentioned above.

The ADC voltage reference input effectively works as a 1 quadrant divider. It thus normalises binary data.
Say, Vcc rises for 10%, the ADC step is raised also by 10%. If a signal is also risen by 10% due to a Vcc jump, it will be presented with a same binary value after ADC.

It sounds like a good trick based on the assumption (generally valid) that the power supply and the signals vary in the same percentage.

This may not be the case in these situations:

1. During ADC conversion time (65us in an ATtiny), the signal is held constant in the sampling capacitor but the reference is changing with the power supply.

2. Non-linearities in amplifier stages cause the percentage in the signal to deviate from the power supply's.

My amplifier is an atttempt a pushing the specs to the limit (fast, low noise) so I'm not taking shortcuts that would be perfectly acceptable in other projects.

[Davor]

If you think about it a bit further, the effects you mention, while completely valid, are of the 2nd order. Your useful signal is falling well under 100Hz. All the interferences above 100Hz will cancel out. Some even improve dithering.