Tinkerer's ( and others ) FPGA backend processor

[moodz]

Imagine if you can sample every transmit / receive pulse every xxx nanoseconds and store the samples in memory so you can do math on them like add / subtract / multiply compare to previous samples etc all in the digital domain.

The FPGA solution will do this. ( as well as generating the Tx pulse train to start with. )

The current FPGA development has the following components.

A 32 bit MIPS like 'soft' processor running at 50Mhz.
Open source code and tools.
A real time operating system. (also opensource )
Serial port
Ethernet option.
16 Mb of RAM
4 Mb of flash
2 channel inbuilt digital CRO so you can align coils / experiment in the field etc.
( this will be a special "PI" CRO ... timing optimised for PI detectors ... like TV CROs used to be made :-) )
A rotary encoder for setting stuff.
Switches and buttons for setting stuff.
LCD display for looking at stuff.

What is needed is a functional 'flowchart' of the descriminating algorithm.

eg the sample at 100uS is subtracted from the sample at 40uS and averaged over 100 pulses. ( I am sure it is more complex than this !)

If we have the theory then the code to make it happen can be created.

Below is the "first run" from the FPGA core processor. ( MIPS32 compatible )

Greetings from the bootloader Feb 23 2010 09:57:59:

Waiting for binary image linked at 0x10000000
Other Menu Options:
1. Memory read word
2. Memory write word
3. Memory read byte
4. Memory write byte
5. Jump to address
6. Raw memory read
7. Raw memory write
8. Checksum
9. Dump
F. Copy 128KB from DDR to flash
>

Regards from moodz.

[Carl-NC]

As part of some R&D, I'm running a PI design with an 18-bit ADC sampling every 2us, which is a lot of information to work with. I would also suggest sticking with a traditional micro instead of an FPGA, at least for initial development.

[Aziz]

Good Application for FPGA

Hi all,

a good application for the FPGA could be implementing a (multiple) integrating ADC. I assume, that it could be clocked with 100 MHz or even faster. Implementing a high precision synchronous counter should be possible. You just need additionally a fast comparator per ADC.

If the gate array is big enough, multiple of integrating ADC's could be well implemented. It is enough to have at least two independent channels.

Aziz

[Tinkerer]

As part of some R&D, I'm running a PI design with an 18-bit ADC sampling every 2us, which is a lot of information to work with. I would also suggest sticking with a traditional micro instead of an FPGA, at least for initial development.

Moods, thanks for the feedback on FPGA.
Honestly, I don't understand anything about it. But somewhere, sometime one has to start learning.

I don't understand anything about PIC's either, but let's see if I can figure out what sampling every 2uS at 18 bit resolution means in terms of a PI.

The most sensitive PI detector that I might be able to build, would give me a 3mV signal amplitude at a distance of 30cm from the coil, for a target with a TC of 5uS.
This is a test target of one half square inch, thin alu foil.

This is the signal at the output of the pramp, that has a gain of 1000.

Therefore, at the input of the pramp, the signal amplitude is 3uV.

Now, if I got my numbers right, 18 bit resolution would be say 1.25V maximum reading divided by 263,144, that is about 4.76uV for the minimum reading.

I think the last 2 bits are a bit unreliable, so the minimum readable signal would need to be about 10uS rounded up.
Lets consider that we have a noise level of 10uS, so the signal would have to be 10uS above the noise level, or about 20uV signal amplitude.

So if my 5TC foil test target gives me 3uV signal at the input of the preamp, I would have to put a gain of about 7 to get the signal within the reach of the 18bit sampling resolution.

I hope this is right. Please correct me if it is not.

With the analog PI, I used a gain of 1000. So what is the deal about having a gain of only seven?

The noise. When I amplify the signal one thousand times with a broad band amplifier, I also amplify the noise 1000 times.

If I only need to amplify by 7, then the noise is so much lower.

So, yeah, I love that 18 bit resolution sampled every 2uS.

Attached is a picture of a decay curve of a 5TC target. It is close to the numbers I used above.

Yes, it is micro volts and nano amps we are talking about.

Tinkerer

[moodz]

As part of some R&D, I'm running a PI design with an 18-bit ADC sampling every 2us, which is a lot of information to work with. I would also suggest sticking with a traditional micro instead of an FPGA, at least for initial development.

Hi Carl ... yeh I have done the initial development on a DSPic but I got sick of the poorly documented processor features and it just wasn' fast enough as Aziz mentions about the fast ADC. ( PICs have hardware bugs too that the manufacturer does not talk about )

I need to run a very accurately timed state machine for the Tx and Rx cycles and you just cant get that out of an microcontroller without falling back to assembly language. The FPGA has goodies like multiple hardware multipliers and +300Mhz dual port memory elements for storing wave samples in.
The 'FPGA programming language' VHDL / verilog needs much less modification if you move to a different FPGA chip. ( cant move from PIC assembly to ARM easily frinstance ... have to rewrite everything ). Best of all if you have a 'circuit diagram' brain you can program an FPGA by simply drawing a schematic in the (free) tool. My first FPGA design some years ago was a frequency counter with not a single line of code written. There are libraries of parts (eg 74XXX TTL and 4XXX CMOS ) as well as plenty of code blocks contributed by the community. No need to figure how they work ... just connect to the virtual pins. I especially like the NO SOLDERING required to change the whole circuit or remap pins ( including physical pins on chip )

I reckon that if you had to start with PICs or the FPGA below you would be up and running faster with the FPGA rather than the PIC.

Check out the user guide for the fpga board ....
http://www.xilinx.com/support/docume...kits/ug230.pdf

This is much better than any microprocessor board I have used and it has everything a test bed PI back end would need for development.

If you dont like the onboard A/Ds then get a demo board from somewhere like www.ti.com .... they have a rather tasty 32bit 4ks/s ADC board for $49 and very easy to connect to FPGA. ( sub 10 nV sensitivity anyone ? )

moodz

[Carl-NC]

Tinkerer,

Usually you want a preamp before the ADC to get the signal level up. Yes, it will also gain up the noise, but then you use averaging techniques to get rid of the noise.

Moodz,

I admit that FPGAs are a weakness for me. I have a Spartan 3 and a Cyclone 3 dev board, but never had the time to mess with them. They certainly do pack a lot of power and features. However, they are considerably more expensive which, for a one-off homebuilt doesn't matter, but does matter for a mass-produced detector.

- Carl

[moodz]

PI backend inbuilt scope .... working

After a few hours of coding ... the scope for the PI backend is working.

Not bad for a couple of hundred lines of VHDL code and not a single CPU cycle used on the CPU. Currently the design is utilising 40% of the FPGA resources. ( cpu, ram, memory controller, flash controller, vga display, ADC capture, serial port )

The display shown is VGA 800x600 with independant control of waveform, grid and text. The CPU can access both text and waveform memory.

The waveform is stored in dual port ram so that it may be simultaneously stored / displayed independant of CPU access to waveform RAM .... very cool.

The wave form ram can store up to 300 Megasamples / sec if required however in this case we are running at 1 msps. ( ie 1 horizontal pixel = 1 uS ) not to be confused with the horizontal VGA rate which is running at 20 nS per pixel. Thus a full unscaled waveform on the screen is 800uS of sample time.

The waveform storage length is 2k words of RAM but can make much bigger if required. The FPGA board is at the lower front of the screen.

The sensitivity is about 5 uV per pixel and the trace here is noise picked up by 10 cm of wire connected to channel A of the ADC.

Moodz

[Qiaozhi]

After a few hours of coding ... the scope for the PI backend is working.

Not bad for a couple of hundred lines of VHDL code and not a single CPU cycle used on the CPU. Currently the design is utilising 40% of the FPGA resources. ( cpu, ram, memory controller, flash controller, vga display, ADC capture, serial port )

The display shown is VGA 800x600 with independant control of waveform, grid and text. The CPU can access both text and waveform memory.

The waveform is stored in dual port ram so that it may be simultaneously stored / displayed independant of CPU access to waveform RAM .... very cool.

The wave form ram can store up to 300 Megasamples / sec if required however in this case we are running at 1 msps. ( ie 1 horizontal pixel = 1 uS ) not to be confused with the horizontal VGA rate which is running at 20 nS per pixel. Thus a full unscaled waveform on the screen is 800uS of sample time.

The waveform storage length is 2k words of RAM but can make much bigger if required. The FPGA board is at the lower front of the screen.

The sensitivity is about 5 uV per pixel and the trace here is noise picked up by 10 cm of wire connected to channel A of the ADC.

Moodz

[ATTACH]11588[/ATTACH]

Very interesting!
But what are the extra symbols shown below?

[moodz]

Very interesting!
But what are the extra symbols shown below?

One of the cool things about FPGAs ( well most of them anyway ) is that you can set what is in the ram when you first fire it up ... unlike most Microprocessor ccts. Those characters are the extended 'block' graphics and are loaded into the ram image that the FGPA fires up with ... mainly because there is no room on the bottom row of chars and also to prove you can write to other lines. The purpose of the characters is to test the Video character rom and display ram is working. The CPU has access to the display ram but currently does nothing as it has only a boot loader and I have not yet written a program to control the PI backend.
The key to FPGA development is to get 'hardware design' ( ie VHDL ) then write application much as you would for conventional microcontroller system. I am offloading all the waveform display work to VHDL logic so CPU will not be tied up.

Moodz

[Aziz]

Hi moodz,

how much is the current consumption of the board? Does it eat more power?
Aziz

[moodz]

Hi moodz,

how much is the current consumption of the board? Does it eat more power?
Aziz

Hi Aziz ... this particular board uses highly efficient switchmode supplies ... I dont think it uses more than about 250 mA at 5 volts. The FPGA feels barely warm .... in fact the dspic I used to use was 2 or 3 times hotter. However the more clocking logic you have in an FPGA as a rule then the more power you use.

[Aziz]

Hi moodz,

Hi Aziz ... this particular board uses highly efficient switchmode supplies ... I dont think it uses more than about 250 mA at 5 volts. The FPGA feels barely warm .... in fact the dspic I used to use was 2 or 3 times hotter. However the more clocking logic you have in an FPGA as a rule then the more power you use.

it would be very interesting, if you could measure this. I appreciate your effort. I know, FPGA's have quite high power consumption. But may be, they have reduced it during the last years.

Nice work. I am looking forward to your results.

Aziz

[moodz]

Very interesting!
But what are the extra symbols shown below?

[moodz]

Hi moodz,



it would be very interesting, if you could measure this. I appreciate your effort. I know, FPGA's have quite high power consumption. But may be, they have reduced it during the last years.

Nice work. I am looking forward to your results.

Aziz

Hi Aziz ... 259 mA using current code. at 5.5 volts .... from plugpack supply. As input voltage goes down then supply current will go up.


Regards,

Moodz.

[Aziz]

Hi Aziz ... 259 mA using current code. at 5.5 volts .... from plugpack supply. As input voltage goes down then supply current will go up.


Regards,

Moodz.

That isn't very much! Thanks for your effort.

Aziz