DEEPER PI DETECTION DEPTH

[Aziz]

G'day Aziz,

The method that finds big chunks of gold of course

For big gold I am leaning toward the longer slower pulse as it will take longer for the eddy currents to build and decay during the on time. The higher the current in the target after the coil current has reached 0 the better well thats my thoughts anyway.

Cheers Mick

Hi Mick,

The method that finds big chunks of gold of course

Then you have to know the answer to the question.

The interesting question is:
What is better? (Or is it the same = no free lunch?)
A saturated long TX pulse or an un-saturated multiple short pulses (TX t-on < TX TC)?

The question is addressed to all members of course. Who want's to win an IQ-award?
(I am biased - I'm not allowed to (win/)loose - what a luck )

Cheers,
Aziz

[Midas]

The oscillation is due to the parasitic capacitance of the coil. ie. inter wire capacitance, coil to shield capacitance and cable capacitance.

I used 200pf parallel capacitance to the 300uH inductance to simulate this.

If you change the simulation for 500pf parallel capacitance, the glitch increases. If you change it to 20pf it disappears.

Tinkerer

OK here's whats happening here, changing the parasitic capacitance of the coil is altering dV/dt which is effecting how much charge is transferred across to the gate of the mosfet, holding it open. Although 20pf of parasitic capacitance seems to make the effect dissapear in actual fact it makes it kick in so fast you don't even notice it. The 500pf actually reduces the amount of charge transferred which slows the time it takes to kick in giving a more obvious dip.

I decided to get a bit more familiar with this Ltspice thing to demonstrate what I'm talking about a bit better. I've got 3 shots in order, the 200pf original, 20pf followed by 500pf.
Trace colours:
Cyan = mosfet gate voltage
Red = gate current
Green=coil current
Notice how the gate voltage hangs around the 4v (gate threshold voltage) to a greater or lesser extent.

[Aziz]

Thanks Aziz,

this is a great help.

While we are at it, could you tell me how to make different inductance coupling:

I have: K1 L1 L2 L3 L4 L5 L6 0.0001, where all inductors have the same coupling. I want to add a Bucking coil, where the k factor is different to the RX coil from the TX coil.

I tried and crashed the LTSpice about 20 times. Could you please help me?

Thanks

Tinkerer

Tinkerer,

just define each coupling coefficient by making more K-statements.
K1 L1 L2 0.0001
K2 L1 L3 0.0001
K3 L1 L4 0.01
K4 L2 L3 ..
K5 L2 L4 ..
K6 L3 L4 ..
..

Note, that if you have n coupled coils, you have to define n*(n-1)/2 coupling coefficients.
n=2: -> 2*1/2 = 1 -> 1 K statement
n=3: -> 3*2/2 = 3 -> 3 K statements
n=4: -> 4*3/2 = 6 -> 6 K statements () (see above example for n=4)
n=5: -> 5*4/2 = 10 -> 10 K statements ()
and so on

Cheers,
Aziz

[Tinkerer]

Tinkerer,

just define each coupling coefficient by making more K-statements.
K1 L1 L2 0.0001
K2 L1 L3 0.0001
K3 L1 L4 0.01
K4 L2 L3 ..
K5 L2 L4 ..
K6 L3 L4 ..
..

Note, that if you have n coupled coils, you have to define n*(n-1)/2 coupling coefficients.
n=2: -> 2*1/2 = 1 -> 1 K statement
n=3: -> 3*2/2 = 3 -> 3 K statements
n=4: -> 4*3/2 = 6 -> 6 K statements () (see above example for n=4)
n=5: -> 5*4/2 = 10 -> 10 K statements ()
and so on

Cheers,
Aziz

Thanks Aziz,

I get the error message: Mutual inductance card missing.

Tinkerer

[Tinkerer]

OK here's whats happening here, changing the parasitic capacitance of the coil is altering dV/dt which is effecting how much charge is transferred across to the gate of the mosfet, holding it open. Although 20pf of parasitic capacitance seems to make the effect dissapear in actual fact it makes it kick in so fast you don't even notice it. The 500pf actually reduces the amount of charge transferred which slows the time it takes to kick in giving a more obvious dip.

I decided to get a bit more familiar with this Ltspice thing to demonstrate what I'm talking about a bit better. I've got 3 shots in order, the 200pf original, 20pf followed by 500pf.
Trace colours:
Cyan = mosfet gate voltage
Red = gate current
Green=coil current
Notice how the gate voltage hangs around the 4v (gate threshold voltage) to a greater or lesser extent.

Thanks Midas,

Now, how do we fix it?

Tinkerer

[Qiaozhi]

OK here's whats happening here, changing the parasitic capacitance of the coil is altering dV/dt which is effecting how much charge is transferred across to the gate of the mosfet, holding it open. Although 20pf of parasitic capacitance seems to make the effect dissapear in actual fact it makes it kick in so fast you don't even notice it. The 500pf actually reduces the amount of charge transferred which slows the time it takes to kick in giving a more obvious dip.

I decided to get a bit more familiar with this Ltspice thing to demonstrate what I'm talking about a bit better. I've got 3 shots in order, the 200pf original, 20pf followed by 500pf.
Trace colours:
Cyan = mosfet gate voltage
Red = gate current
Green=coil current
Notice how the gate voltage hangs around the 4v (gate threshold voltage) to a greater or lesser extent.

Actually, the real problem seems to be in the inductor model. The 200pF capacitance is in parallel with the inductor and its DC resistance, but it's an ideal capacitance model. i.e. no series resistance. This causes a huge current spike to appear across the inductor model when the mosfet (or switch) turns on.

I removed all parameters from the inductor, except the inductance of course; and inserted a resistor (3 ohm) in series with the coil with a capacitor (200pF) across it. In all cases - with or without mosfet - the glitch has disappeared.

However, as Carl discovered, there are some glitches there in practice, which implies that we need a more complex model, to make sure simulation matches reality. There most likely needs to be at least a capacitor for inter-winding capacitance and for the connecting cable, etc. ... but don't forget all the other parameters on the capacitor (such as equivalent series resistance and inductance; and equivalent parallel resistance and capacitance).

Obviously there are some issues with charge across the gate of the mosfet, but that's not the whole story. Have a look at the attached simulation, and you'll see the glitches are not there. The bottom line is that there's no way to add an equivalent series resistance to the parallel capaitance in the inductor properties. The best way to solve this would be to create a subcircuit for the coil, and not rely on the LTSpice model alone.

[Carl-NC]

what is better:
Wasting high power for a long pulse duration (saturated TX coil current) or
wasting low power for multiple short pulses (collecting the signal response over multiple short pulses)?

Unfortunately there are advantages to either. E.g., what's better, a large coil or a small coil?

[Carl-NC]

The expression "saturate" is often used, it could be changed to another expression often used,"fully charged", which is just as wrong, to say the the eddy currents have reached a maximum level.

In traditional PI, people use "fully charged" to actually mean "fully discharged." That is, the "on" eddies have died out.

[Carl-NC]

Now what if we were able to make a current pulse that is square wave, rather than the current pulse that we end up with, with the resistor in series with the coil.

So-called "constant-current PI" has some distinct advantages, and I urge folks to take a closer look at it. However, the series R is not the preferred way to do it.

[Qiaozhi]

Now you see it, now you don't!

Here's a little mystery for you:
By the way, I'm not trying to be mysterious ... I don't know the answer either.

Have a look at the attached simulation. The left-hand circuit uses the standard LTSpice inductor model with a series resistance parameter of 3 ohms and a parallel capacitance parameter of 200pF. Whereas the right-hand circuit (a direct copy of circuit 1) has been modified, with the LTSpice inductor model having only the inductance value specified, and the series resistance and parallel capacitance realised with discrete parts.

Theoretically there should be no difference in the simulation results ... but there is!

At 10us, when the mosfet is turned on, there is a small glitch in I(L1), and two other glitches after the mosfet is turned off. However, none of these gitches are present in I(L3).

Why?????

You can try removing the zener diodes across the mosfets if you wish, but it just makes the glitches bigger.

Something for you to ponder over.

P.S. Just noticed that I used a conventional diode symbol for the zener, but that's just a visual problem as it still works correctly.

[Qiaozhi]

By the way, it's nothing to do with the mutual inductances between L1 and L3 to targets L2 and L4. I've just tried deleting them both, and the results are the same.

[simonbaker]

=Supply current/voltage


=Supply frequency

A target (coil) has an impedance, which is frequency dependent.

Aziz

PS: To see the induced voltage behaviour at the receiver coil, just replace the I(L3) by d(I(L3)). d() is the first derivation of the term in brackets.

PPS:
A high stimulation frequency will lead to a lower target eddy current (due to impedance). On the other hand, the RX coil would see more induced voltage due to higher eddy current change dI/dt.
So, where is the free lunch?

I feel you really have to include the receiver coil dynamics in the simulation, you can't just assume things. Every component of a dynamic system has an effect. It is true that some effects may be negligible due to scale, but to be sure we should model everything; at least it would satisfy the "show me" people, like me.

Cheers,

-SB

[simonbaker]

Here's a little mystery for you:
By the way, I'm not trying to be mysterious ... I don't know the answer either.

Have a look at the attached simulation. The left-hand circuit uses the standard LTSpice inductor model with a series resistance parameter of 3 ohms and a parallel capacitance parameter of 200pF. Whereas the right-hand circuit (a direct copy of circuit 1) has been modified, with the LTSpice inductor model having only the inductance value specified, and the series resistance and parallel capacitance realised with discrete parts.

Theoretically there should be no difference in the simulation results ... but there is!

At 10us, when the mosfet is turned on, there is a small glitch in I(L1), and two other glitches after the mosfet is turned off. However, none of these gitches are present in I(L3).

Why?????

You can try removing the zener diodes across the mosfets if you wish, but it just makes the glitches bigger.

Something for you to ponder over.

P.S. Just noticed that I used a conventional diode symbol for the zener, but that's just a visual problem as it still works correctly.

Hi Qiaozhi:

I think reason is: you are comparing the currents in the coils, rather than the currents into the coil equivalent networks.

If you put a .000001 ohm resistor in the circuit branch to the discreet model, and compare the current through that to the current through the first coil (lumped model), the currents match up better.

-SB

[simonbaker]

G'day Simon,

Well my thoughts on this are that although case 1 has a higher current change in the target, the problem is once the turn off current has reached 0 and we are able to sample the target only has 250uA compared to the 650uA in the target that had the flat top(case 2) We are only able to measure the signal during the off time conventionally but if something can be worked out to sample during the flyback and reject ground response well then case 1 would win.

Now what if we were able to make a current pulse that is square wave, rather than the current pulse that we end up with, with the resistor in series with the coil. We would have a fairly rapid rise at tx turn on and once the desired current is achieved(say 3A) we then hold it at that for(200uS) and then turn it off. This will give enough time for eddie currents in larger targets to settle before turn off. A switch-mode power supply would be ideal to drive this to minimize losses. Yes this will use more battery power, but who cares, li-ion batterys are cheap and light and if I'm finding more gold it will worry me not

Cheers Mick

Yes, I guess the absolute levels affect the detection from a practical standpoint and I'm not familiar enough with the PI circuits to see how that factors in. It just seems that theoretically the big jump would be the key signal, but I'll have to get more up on PI circuitry.

Your idea for fast turn on sounds good in theory; in fact, to make that current square wave you pretty much have to create a huge voltage spike at turn-on similar to the flyback voltage; you'd actually then get two big kicks to work with. Maybe there are PI designs that essentially work with dual kicks in opposite directions like that.

-SB

[Tinkerer]

By the way, it's nothing to do with the mutual inductances between L1 and L3 to targets L2 and L4. I've just tried deleting them both, and the results are the same.

Try the attached sim, the effect is still there.

It definitely has to do with the model and I think the model is correct. I also think that Midas has shown the cause, but how do we fix it?

We want a Spice model that is as similar as possible to a real detector. As Carl's post shows, this glitch really exists. A 100 Ohm resistor fixes this glitch, but brings other problem with the switching of the Mosfet.

Can anybody come up with a good Mosfet drive simulation model?

These sims show a target response on the target level. Now we want to get these responses to the pre-amp. I have used a large coupling factor from TX to target, so we can easy see the response. However, the coupling is in fact very much lower.

Then we want to represent an RX coil and a Bucking coil for an IB coil assembly.
Once e have all the individual parts modeled, we can then see how differences in the assembly or sizes or inductance change the shape or behavior of the target response and RX signal.

Along the way, this can answer many questions, as seen with the TX current glitch seen above.

Tinkerer