Let's made a PC-base metal detector with usb interface !!!

[Carl-NC]

Aziz,

I've been trying to keep up with your project. Let me see if I understand what you are doing... you want to feed multiple samples to a PC via the audio card... then I guess you are going to use the PC to process the data. Is that right?

Are you using a modulated scheme to get all the samples on to one analog line to the audio card? Seems like a lot of work. What was wrong with a TDMA approach? Or, why not put the ADC on the board and use the PC parallel port to grab data? It's been a very long time since I've done parallel port data transfer, maybe it's too slow... if it is, maybe a SCSI card would be a good solution.

Anyway, it's all interesting!

- Carl

[Aziz]

Hi Carl,

Aziz,

I've been trying to keep up with your project. Let me see if I understand what you are doing... you want to feed multiple samples to a PC via the audio card... then I guess you are going to use the PC to process the data. Is that right?
- Carl

that's correct. The sound cards today are excellent and cheap, achieving a super high resolution, high speed and low noise. I had already good experiences with them due to former IB-VLF project. Now eliminating all the disadvantages of the former project with a PI type platform (removing as much frequency domain effects as possible).

It is the base for lots of PI experiments. Therefore I need the raw channel data in my PC. But the implementation must be a poor-man's solution. Using the HD sound card and pure analog audio interface seems to be the cheapest and easiest one for me.

Once the channel data is available to the PC software, a better discrimination and ground balancing could be developped. Furthermore, it makes sophisticated methods like boxcar averaging, lock-in amplifier, digital filtering, etc. possible. So the ADC resolution can be increased even furthermore.

Aziz,

Are you using a modulated scheme to get all the samples on to one analog line to the audio card? Seems like a lot of work. What was wrong with a TDMA approach? Or, why not put the ADC on the board and use the PC parallel port to grab data? It's been a very long time since I've done parallel port data transfer, maybe it's too slow... if it is, maybe a SCSI card would be a good solution.

Anyway, it's all interesting!

- Carl

The first modulator was designed to pass four channels through one audio line. The other line was determined for control signalling. The new modulator now is a stereo channel modulator, which only passes two channels per line. The ADC resolution won't be limited much in this case and both ADC's in the sound-card will be used in the same time (stereo mode). The purpose of the modulator is simple: The sound card accepts only AC signals. The DC sample signals must be converted into AC signals and combined all together, which can be sent through the transportation line.

The modulation is a pure triangle amplitude modulation. Each channel will be modulated independently on different frequency and will be mixed and filtered before passing them to the sound card. The demodulation will be done in the PC software (laptop) using either lock-in amp or FFT and will reconstruct the channel data spread in the modulation frequency harmonics. The modulation frequency and cycle frequency will be sent through the sound card output. This ensures exact synchronisation of two different systems and makes lock-in amps possible. The errors for the transportation of the modulated signals will be low due to very sharp digital filtering methods.

I have decided using a pure analog audio interface for different reasons:
- PC industry develops the ADC/DAC part for me (low risk)
- makes development easy, fast and very cheap
- easy available and replaceable components (modular components)
- high resolution, high speed, low noise
- easy upgradeable with future components
- I have already several HD sound cards and a laptop!

Combined with the huge processing power of the PC (laptop), one can do lots of more with the flexible software programming.

All other modulation types or other interfaces will cause many problems or cost's. That isn't what I want and I can't effort. I have very limited resources and it must be a pure poor-man's solution.

Once realized a minimal PI platform and solved all inherent problems, we can probably expect some interesting surprises. But only few people seems to see the big advantages herein.

The modulator is finished now and I am going to develop the other trivial hardware parts. Particularly, the PC software will be the most non-trivial part of this project. There is still lots of work to do.

Aziz

[Aziz]

Hi all,

I have tested the new stereo channel modulator with the USB HD sound card from Creative (Xmod). I am fully satisfied at the moment. It gives superior channel acquisition at the ground noise levels between -104..-110 dB (depending on the modulation frequency). As this device has a low pass filter on the input/output at the corner frequency of appr. 21 kHz, the max. modulation frequency can be set upto 18 kHz. The channels s1/s3 can be sampled at 4.5 kHz and 13.5 kHz (22.5 kHz will be attenuated). The channels s2/s4 only at 9 kHz (27 kHz will be attenuated). This device should be operated on lower modulation frequencies ( <= 12 kHz).

There are some better HD sound cards which allow a higher modulation frequency and lower noise.

The op-amps in the channel modulator create some level of voltage offset error and noise (can be detected and measured in the laptop software and be removed from the calculation => automatic correction). The TL072 op-amps are working quite well and the noise level is acceptable.

For the rest of the PI board, I will need 8 op-amps for the 4 channel S&H, one for the gated integrator, one for the PGA and one for the pre-amplifier. Total: 11 op-amps to be needed more. The S&H op-amps will be a dual JFET op-amps. All others single type.

The total current consumption of the project is 66 mA/12V at the moment. I hope, the rest of the design will not exceed the 200 mA limit and also the DC/DC converter delivers enough current for proper operation. The transmit pulse power will be added later into the calculation.

Aziz

[Aziz]

Hello friends,

I want to propose the following programmable gain amplifier for this project. It is an inverting type, which amplifies the target signal from the pre-amp. It uses three control lines:

PGAgate:
off (-5V): Forces the PGA to zero output for software adjustments (offset voltage errors) and avoiding the saturation of the PGA op-amp. When the gate JFET is off, it is a typical voltage follower for ground (zero volt).
on (0V): PGA works

PGA0, PGA1: Switches the different feedback resistors for different gains. Keep attention, that this amplifier inverts the input signal.

The reason for the inverting type of PGA is as follows: The JFET's can be switched easier due to inverting input pin of the op-amp (pin 2), which is a virtual ground potential. The source pins of the JFET's are connected to this virtual ground potential. A voltage of -5V on the JFET's gate switches the JFET's off, and 0V on.

The PGAgate (input JFET gate) has also a temperature compensation function. The Rdson (switch-on resistance of JFET) will have then same temperature behaviour on both feedback and input path, which are compensating temperature dependend amplification drift. Of course, if I would have more control lines, I would offer J1 a seperate control line. But I have to save control lines. Four different amplification factors should be enough at the moment.

The input resistance of the PGA is 1k (=R30). The reverse transfer capacitance of the JFET's (Crss = 5pF) will limit the bandwith slightly. It is also a welcoming effect of reducing high frequency noise. It is anyway reduced by the 47pF capacitor (C10) in the PGA.

The amplification factors (feedback resistors) may be changed during the development. It depends on the pre-amp amplification and other factors.

Aziz

[Aziz]

Hello friends,

here is the next proposal for this project: gated integrator with clear. The schematics below is a classical gated integrator circuit. J2 is to compensate the temperatur behaviour of J4 (gate) and can be omitted, if you want to save parts (J2 is always switched on). J3 discharges the integrated voltage, held in the holding capacitor C9 (Cint).
The integrator needs two control lines: Integrate/Hold and ClrInt (Clear).

The parts value of R18, C9 and R4 may be changed later. The input resistance of the integrator is 1k ( = R18 ) .

The 100Meg resistor is only for SPICE simulation and helps to convergate. This will not be used in the circuit.

The integrator is an inverting type. So the PGA and integrator together is a non-inverting circuit now.


Aziz

[Aziz]

Some notes on the discharging resistor R4 of the previous schematics:

R4 is a place holder in the circuit for the case of beeing set to a high impedance resistor (10k - 100k). Normally, discharging resistor R4 can be omitted due to Rdson of J2 and J3 (~200 Ohm together).

The high impedance version is for a different operation mode reserved (auto discharging with time constant T = R4*C9). This makes the design more flexible for future developments.

Next topic: Sample and Hold (S&H) stages. You can bet on, I am gonna to use same JFET's!

Aziz

[Aziz]

Hi all,

now the S&H gets a bit non-trivial and tricky. I do not want to use integrated circuits for this stage (difficult to get these IC's). I will develop an application specific discrete S&H with optimized performance for PI technology. It should have a fast settling time (must be a open-loop type) and a minimal droop rate. It should provide 0/-5V control switching. The voltage offset errors will be compensated in the software of course (less critical demand).

As I haven't anymore a virtual ground on the source pin of the JFET, care must be taken for switching voltage potential (gate voltage). The pre-amp will be a non-inverting amplifier with high impedance capability. The PGA and the Integrator will generate a positive rail target signal level. As this signal level exceeds the +1.2V range, the JFET's aren't sampling (switching) anymore. Therefore I will invert the target signal level into the negative power supply rail and can switch more signal level range at the end. The samples s1..s4 will be pure negative voltage level and can be processed by the modulator with ease.

Minimal negative target signal level up to -1V is allowed. Maximal positive signal level should be in range of +2 .. +3 V (op-amp saturating at roughly +3.5V). Taking these compromize by definition, the S&H circuit becames simple and will have a good performance and speed.

Maybe I can find a better solution in the mean time. I will publish my S&H circuit proposal next time.
Take care,

Aziz

[Aziz]

Hi all,

during reading the good comments from bbsailor (topic: eddy currents), I thought of about an interesting application, which can also be realized.
An alternating (interleaved) transmit pulse width with two different TX-on times (note: patent infringement - only for personal use). Target signals will be sampled alternatively into s1/s2 (left channel) and s3/s4 (right channel). This gives the option for determining the TC of the targets better or detecting for short TC's and long TC's targets simultaneously with the cost of half PPS rate (we have really enough).

There are many other options possible with this universal experimental design.

Aziz

[Aziz]

Hello friends,

now the sample and hold design is finished. The schematics below shows only one channel. Same applies to the other channels s2, s3 and s4. I strongly recommend to use a dual JFET op-amp (TL072, TL082 or others).

The channel output voltages s1, .. s4 will be on the negative rail level. The holding capacitor Ch (2.2nF) must be optimized for fast settling and low droop rate later. As the modulator has an input impedance of 47k, the passive lowpass filter has enough low impedance. The lowpass filter minimizes further noise and voltage settling swings.

That was the most important functional parts of this design. Now, the microcontroller with the PI front-end (coil driver + pre-amp) is missing.

It is again time to fire up the soldering iron.

Aziz

[Aziz]

Hi all,

I found the following important warning about the JFET's in the internet (see below). If you want to try other configurations, then be aware of this warning. The used gate logic voltages in this project are allways below 0V (0V/-5V). Then a reverse biased diode can be omitted and makes the circuit simpler.

Of course, the JFET can be operated with positive gate voltages to lower the Rdson. The gate current must be limited in this case.

Aziz

[Aziz]

Hi all,

I have a passion to the JFET's! They will be used further. But other ultra low noise types in the pre-amp stage (I hope, I can get the JFET's anywhere). I am planning to use a combined JFET and op-amp based pre-amplifier. With some good matched parts, we can fall short of the 1nV/sqrtHz noise density level. This part will be the last of all and I have to read lots of technical stuff till then.

Aziz

[bbsailor]

FET Design Idea

Hi all,

I have a passion to the JFET's! They will be used further. But other ultra low noise types in the pre-amp stage (I hope, I can get the JFET's anywhere). I am planning to use a combined JFET and op-amp based pre-amplifier. With some good matched parts, we can fall short of the 1nV/sqrtHz noise density level. This part will be the last of all and I have to read lots of technical stuff till then.

Aziz

Aziz,

Your above statement stimulated the following idea.

Bias a FET to serve two of the following functions.

1. Be a switched off gate so that during the TX and flyback pulse the RX coil is clamped off eliminating the need for two clamping diodes.

2. Be quickly switched on and become a low 10X gain preamp to become the first RX coil amplifier stage and eliminate/minimize the cable capacitance to allow faster sampling in later stages.

If something like this could be designed and embedded into DD coil housing, it could make PI coils active and improve a whole new class of coils. What you would be trying to do is switch the FET between the function of the clamping diodes and then quickly become a low gain active RX coil amplifier. This could then feed a lower gain opamp stage that would have a wider bandwidth with a lower gain of about 100.

Good design practice places the lowest noise devices as close to the signal source as possible to improve the overall signal to noise ratio. The secondary benefit is improving the RX coil potential sampling speed by eliminating/minimizing the coax capacitance on the effective value of the RX damping resistor.

The design constraints are:

(1) Any components that are chosen must be small enough not to allow eddy currents to be generated in them and to maintain the balance of the coils.

(2) The FET module should have a small footprint and not have any circuit board traces that could form a loop that would appear larger to the eddy currents.

(3) The TX pulse should provide the blanking pulse to turn the FET into switched off gate with a slightly extended time to accomodate the flyback pulse decay time of a few microseconds. The connection for this TX gate switch could come from inside the coil housing directly from the TX coil.

(4) Power for the FET could come from the a rectified and filtered TX pulse or from phantom power on the RX coax or from an additional wire.

Model, design and prototype this circuit and every PI coil maker could use it to improve the performance of their DD coil machines.

Prove that this works, select the appropriate circuit components, design a miniature circuit board and show how it would work with most DD PI circuits/coils and you will have a good, universal circuit improvment.

If it works on a DD coil, a mono coil version could be explored that would need to handle higher power.

I hope this stimulates your thinking and we get some contributions from forum members.

bbsailor

[Aziz]

Hi bbsailor,

I did already some circuit simulation experiments but haven't found a satisfiying solution yet. The anti-parallel clamping diodes are still the best solution at the moment until I have more time at later stages of the project. I also have to get some spice models for high voltage FET's with lower capacitances (high voltage, small signal FET's) to continue the work. As you surely have noticed, I am working in a reversed order.

Damping process is quite critical part and parasitic capacitances, which will be added from the front-end blocking FET's, will have severe negative effects. I will think of later, how I can improve something on this. But I would need a running PI platform then. Taking the preamp and damping process to the coil housing is really a good idea.

Aziz

[Aziz]

Hi all,

I will show you the current state of this project:

First photo: my former modulator
Second photo: my new stereo modulator and power supply module
Third module: new modulator with some descriptions
Aziz

[simonbaker]

wiring

Hi Aziz:

Can you show the underside of one of the boards and describe how you wire the parts together? I'm interested in how feasible it is to build circuits without making a PCB, what the effort is, etc.

Very nice work.

Regards,

-SB