Multilayer PCB coils viable?

[lucifer]

I've made these double sided with interleaved spirals.

Teleno,
Do you shield that one and if yes what do you use for shield?

[ahermida]

This is how I shield my PCB coils. I use the shells made by @dbower. The inside of each shell is painted with guitar shielding ink (make sure to leave a thin strip without shielding on each shell. To connect a wire, just place the wire on top of the painted shell and put a dab of paint. Once the paint dries, the will stay in place and conduct. Each shield connects to the same pad on the PCB coil and then connect a wire to the outside (shown in gray). The other pad is the signal (shown in red). I use double sticky tape with foam to place the PCB on the inside of the bottom shell so it doesn't move around. This approach is NOT waterproof but I wasn't going for that. I just wanted to test the coil with the Sand Shark.

I connected this coil to a Tesoro Sand Shark with a damaged coil and it works like a charm.

A.

[Gunghouk]

Wow! Thank you guys for some great info and pics.
From all these previous trials a number of questions arise.

From basic principles :
capacitance =(Eo.Er.D)/A
where
Eo = the permittivity for a vacuum = 8.854E-12
Er= the relative permittivity of the board material (4.5 worse case?)
D= distance between plates(tracks)
and A = the area of facing surfaces (Track thickness x total track length)

Resistance R = (Length/Cross sectional area) * material resistivity

So increasing track thickness and/or width will reduce resistance but increase adjacent track capacitance as the adjacent track facing area increases (assuming top and bottom tracks don't run on top of each other) and neglecting fringing capacitance between top & bottom tracks. Longer total track length will increase inductance but is bad for R and C.

For speed of sampling and low conductivity sensing low capacitance is desirable correct?
For higher transmitted power low resistance is desirable correct?

So where is the best tradeoff? Is there a solution? Would tinning the tracks help with resistance or create a boundary or 2 lane highway so to speak?

Of course filled vias are assumed throughout

Please keep up this fascinating discussion

P. S.
There a lots of spiral length calculators like this online for further analysis.
https://www.omnicalculator.com/math/spiral-length

[Teleno]

Teleno,
Do you shield that one and if yes what do you use for shield?

Resostance is too high for the intended use in a PI. I'm keeping it for my pulse-biased oscillator project.

https://www.geotech1.com/forums/foru...ed-oscillators

The hand wound spiral coil in my PI is shielded as ahermida described and I would do the same with a PCB coil.

[F117]

Teleno :

I made these double sided with interleaved spirals.

I once had a go on 2x a single layer PCB coil in series stacked on top of each other...

https://www.geotech1.com/forums/foru...oils-in-series

Thanks to mutual inductance, the overal measured inductance = 3x the inductance of a single coil.

[Gunghouk]

Teleno :

I once had a go on 2x a single layer PCB coil in series stacked on top of each other...

https://www.geotech1.com/forums/foru...oils-in-series

Thanks to mutual inductance, the overal measured inductance = 3x the inductance of a single coil.

Fascinating, thanks for sharing. This is almost the configuration I would try first but on a single, double sided board which should increase the mutual coupling with only the thickness of the single board to contend with rather than 2 boards. Capacitance could be kept to a minimum with alternate upper lower track positioning and a shorter total track length would reduce resistance with the gain in inductance to get the 300-400uH range. Excellent news.

Could any of this be confirmed in a simulation, LTspice?
Thanks for everyone's input.

Neil

[Gunghouk]

Another thought, couldn't you design the ultimate balanced DD coil what with the predictable manufacturing tolerances in a PCB design? Top layer one coil, bottom layer the other or similar multilayer geometry.
ie. Interleaved coils, layers 1 & 3 = coil A, 2 & 4 = coil B or does one need to be on top of the other?

[Carl-NC]

Could any of this be confirmed in a simulation, LTspice?

Spice does component-level simulation. For field simulations you need an FEM (finite element modeling) simulator that can do electric & magnetic fields.

Another thought, couldn't you design the ultimate balanced DD coil what with the predictable manufacturing tolerances in a PCB design?

Yes, once you got the coils balanced, every PCB coil from then on would be exactly the same.

[pito]

tolerances in a PCB design?

If out of balance is less than 3V this circuit will compensate that.