@baum7154
technically it is not possible make VDI samples gap below 10us (even on 2,7MHz ADC clock). Real VDI samples gap in the v121 was 32,5us. (20us took conversion with 1,7MHz ADC clock + fixed in the code 12,5us)
More details in the changelog.txt[/QUOTE]
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dantech,
I am a bit confused by the phrase 'VDI samples gap'. Please explain what a VDI samples gap is. Are you talking about the main sample window width or possibly the window duration?
When I look at the scope trace of my V1.2.1 Chance the main sample delay at a minimum Guard Interval setting of '10', the sample delay with the original clock of 11.0592mHz, starts about 9us after the coil begins its flyback. The duration or width of the main sample window is 12.5us, after this the window closes. I do not see any other real delay of 20us on the scope.
Also using Google Translator I am unable to open your link and there is a message that there is no file.
Thanks
Dan
technically it is not possible make VDI samples gap below 10us (even on 2,7MHz ADC clock). Real VDI samples gap in the v121 was 32,5us. (20us took conversion with 1,7MHz ADC clock + fixed in the code 12,5us)
More details in the changelog.txt[/QUOTE]
--------------------------------------------------------
dantech,
I am a bit confused by the phrase 'VDI samples gap'. Please explain what a VDI samples gap is. Are you talking about the main sample window width or possibly the window duration?
When I look at the scope trace of my V1.2.1 Chance the main sample delay at a minimum Guard Interval setting of '10', the sample delay with the original clock of 11.0592mHz, starts about 9us after the coil begins its flyback. The duration or width of the main sample window is 12.5us, after this the window closes. I do not see any other real delay of 20us on the scope.
Also using Google Translator I am unable to open your link and there is a message that there is no file.
Thanks
Dan
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