New Bipolar Boost TX and Front End

[Altra]

@Mdtoday and others that may be interested. I have made some improvements that will be incorporated into version 2 of the TXRX board. The improvements accomplish the following. (1) A more desireable and flatter constant current waveform, (2) a much faster (about 2x) current transition from full on to 0, (3) complete redesign of the MOSFET driver using an ADuM4120. This eliminates the toroid pulse transformers and reduces the parts count per MOSFET driver from 12 down to 4. (4) Reduced propagation delays for the MOSFET drive.

The HV boost section has slightly added complexity by eliminating MOSFET body diode charge path for the boost storage capacitors. A diode is required between the coil and the boost MOSFET(s) to isolate the capacitance in the MOSFET drive from the coil. Additional steering diodes are needed to suppl the flyback voltage to the boost capacitor. Also the flyback voltage is "stacked' onto 15V, thereby overcoming the usual loss of boost, allowing boost up to 1 amp in less than 5 usec. The two HV boost capacitors are reduced to 0.022uF which is readily available in higher voltage ratings and smaller footprint (200V vs 100V for the 0.22 and are available in 1206 package).

The signaling for the MOSFET(s) is more straightforward (and more like everyone is used to seeing)... no more start and stop signals for each function. The pin count needed for interfacing with the logic board is reduced by 4.

The simulation files are in [ATTACH=CONFIG]48705[/ATTACH]

There are two versions of the simulation schematic:
TX(ADuM)_RX(THAT).asc : new TX with THAT RX
TX(ADuM)_RX(dual JFET).asc : new TX with dyul OPA828 JFET(s)
the ADuM.asc is not a separate simulation schematic, but is a subsheet used by both simulations

I believe I have included all of the needed symbols and subcircuits, but let me know if any turn up missing.

These improvements will not be incorporated into the PCB set until we are done with our testing of the current hardware. Also we will probably move to a 20 bit ADC in version 2.

JL looks like a real a improvement and simplification! Can't wait to try it out.

Thanks for posting

[KingJL]

... mcemos.lib& 74HC.lib are missing

I believe that mcemos.lib is unused so the spice statement ".lib mcemos.lib" can be deleted. I have incuded the 74HC.lib in the new zip... I forgot that spdt.sub included the 74HC.lib.

... but the sim shouts Timestep too small schmitt instance TX(ADuM)_RX(THAT))

I made a change to the capacitor size in the ADuM subsheet that should help with that ... reduced it to 3.3uF... seems to make the initial 2 cycles run quicker and smoother. You need enough capacitance to supply the gate voltage for the longest required period (in our case it is the damp signal) but not so much that it causes other issues in the first 2 cycles. I tried 1uF... this worked but caused excessive droop in the damp signal. 2.2uF worked well for our current parameters, but for long PRT's droop re-appeared. 3.3uF seems to work just fine.

Make sure that LTSpice is the latest... my latest version is LTSpiceXVII, Nov 7, 2019. Set Simulate>Control Panel>SPICE>Solver =Normal, Also in Simulate>Edit Simulation Command set "Startexternal DC supply voltages at 0" checked... all other checkboxes unchecked. Make sure that the spice statement ".optionGmin=1e-010" is not commented out. I think it works withGmin set to 1e=011, albeit much slower. With Gmin set todefault ( 1e-012 ), Time step too small errors occur. It isworking in my environment with the above settings.

Newzip with 74HC.lib included, ADuM corrections, and mcemos.lib statement deleted.

[KingJL]

... I will study the simulation and familiarise myself with the ADuM4120...

Now the leading edge TX current can be fine tuned by the kw ( boost width) timing parameter and the max TX current can be tweaked with the +5V ( Vcc parameter). Max TX current course tuning is by R14 in the sim (R6, R7, R8, R10 in the actual circuit). This will easily translate into the actual hardware setting/parameters.

Since we no longer require the 3.3V supply to the interface board, can the 3.3V supply on the the PS/battery board be reconfigured to supply the 5V for the Nextion display?

In your original testing of the PS, what was the actual current limit for the 20V? What would be your thoughts on disabling the boost regulator during the first 80 usec of the RX period. I am thinking we can do away with our S3 sample and accomplish everything we need with S0 (2 us after damp & RX unblock), S1 (15 usec after TX off), and S2 (30 usec after S1 or in this case 45 usec).

[Mdtoday]

Now the leading edge TX current can be fine tuned by the kw ( boost width) timing parameter and the max TX current can be tweaked with the +5V ( Vcc parameter). Max TX current course tuning is by R14 in the sim (R6, R7, R8, R10 in the actual circuit). This will easily translate into the actual hardware setting/parameters.

Since we no longer require the 3.3V supply to the interface board, can the 3.3V supply on the the PS/battery board be reconfigured to supply the 5V for the Nextion display?

In your original testing of the PS, what was the actual current limit for the 20V? What would be your thoughts on disabling the boost regulator during the first 80 usec of the RX period. I am thinking we can do away with our S3 sample and accomplish everything we need with S0 (2 us after damp & RX unblock), S1 (15 usec after TX off), and S2 (30 usec after S1 or in this case 45 usec).

Thanks for the update JL, looking great!

Yes, the 3.3v reg can be replaced with a 5v version for the Nextion supply, great idea.

The original 20v PS testing load was 150mA which is the max output limit for the post regulator.

I had included an extra footprint to allow for another output capacitor on the 20v switch mode supply and we should be able to carefully lift pin 4 (enable) of the MT3608 for testing as isolating pin 4 by cutting tracks would be difficult as it is on a large fill zone.



Like the idea of disabling the boost though, I think it will work.

[KingJL]

The original 20v PS testing load was 150mA which is the max output limit for the post regulator.

Great... the 15V for the re-configured TX draws < 15mA. The 20V also draws < 15mA. So I think we can use the 20/15 volt circuits as they are with maybe a little bit of tantalum storage for the 15V line. The total draw on the 20V should be around 50mA when you take in consideration the 15V regulator.

Like the idea of disabling the boost though, I think it will work.

Do you want to follow through and test that feasibility or do you want me to do it?

[KingJL]

Now the leading edge TX current can be fine tuned by the kw ( boost width) timing parameter and the max TX current can be tweaked with the +5V ( Vcc parameter). Max TX current course tuning is by R14 in the sim (R6, R7, R8, R10 in the actual circuit). This will easily translate into the actual hardware setting/parameters.

For example, the TX(ADuM)_RX(THAT) simulation as was delivered in the last zip and : R14=1.55, Vcc=5.026, kw=4.32u, dw=2.87u, and the ".option Gmin=1e-010" commented (using the Control Panel Spice default of 1e-012) results in the following waveform taken at around the 29 ms mark.

I don't think that for practical purposes, you can get much more flatter/balance than that!

[KingJL]

...Do you want to follow through and test that feasibility or do you want me to do it?

I can provide timing sgnals at the PMOD J4 if you tell what you would require.

[KingJL]

I can provide timing sgnals at the PMOD J4 if you tell what you would require.

I could send out a 3.3V blanking pulse during the time that we want the boost reg disabled... starting at TX (to let the 20V stabilize prior to RX) and extending into the RX for for 20% of the PRT (boost reg disabled for the 1st 30% of PRT). You could the use AND logic to control the regulator... enabled except for when a "blank" signal from PMOD J4. That way it is running by default.

[Mdtoday]

For example, the TX(ADuM)_RX(THAT) simulation as was delivered in the last zip and : R14=1.55, Vcc=5.026, kw=4.32u, dw=2.87u, and the ".option Gmin=1e-010" commented (using the Control Panel Spice default of 1e-012) results in the following waveform taken at around the 29 ms mark.
[ATTACH=CONFIG]48714[/ATTACH]
I don't think that for practical purposes, you can get much more flatter/balance than that!

yes, looks great

[Mdtoday]

I could send out a 3.3V blanking pulse during the time that we want the boost reg disabled... starting at TX (to let the 20V stabilize prior to RX) and extending into the RX for for 20% of the PRT (boost reg disabled for the 1st 30% of PRT). You could the use AND logic to control the regulator... enabled except for when a "blank" signal from PMOD J4. That way it is running by default.

Yes, i think this is a good approach, we should try this.

[Mdtoday]

On replacing the 3v reg with 5v, I thought that family of LDO devices had a 5v version....they don't but I think I have found a replacement for the current PS board.

We can always up-rev the board once everything is tested and settled.

Just noticed too, that we need to change values of the PP input voltage divider resistors as they are tied to 3v3 rail at connector, maybe a zener to replace R4?...or just change R value

[KingJL]

... We can always up-rev the board once everything is tested and settled.

I agree!

Just noticed too, that we need to change values of the PP input voltage divider resistors as they are tied to 3v3 rail at connector, maybe a zener to replace R4?...or just change R value

I am not sure we need to quite do that any longer... as we are using the Nextion gpio pin interface for PP now. I think you have interfaced a PP push button switch to the Nextion gpio in other projects... we can do it the same way!

[KingJL]

I could send out a 3.3V blanking pulse during the time that we want the boost reg disabled... starting at TX (to let the 20V stabilize prior to RX) and extending into the RX for for 20% of the PRT (boost reg disabled for the 1st 30% of PRT). You could the use AND logic to control the regulator... enabled except for when a "blank" signal from PMOD J4. That way it is running by default.

I believe that we could get away with disabling the boost reg at TX_OFF... and only blank for 20% of PRT from TX _OFF. I will work on implementing that in the FPGA. I will supply a blanking pulse to PMod J4 (probably pin 3).

[Mdtoday]

I agree!I am not sure we need to quite do that any longer... as we are using the Nextion gpio pin interface for PP now. I think you have interfaced a PP push button switch to the Nextion gpio in other projects... we can do it the same way!

Yes, of course, we just use the expansion port inputs as I have done previously...

I have also identified a few linear 5v regs we can use, they have an error flag output on pin 5 in place of sense input so we can leave it floating or snip off the lead for testing on current pcb. Microchip/TI have similar.

http://ww1.microchip.com/downloads/e...S20005685B.pdf

Next rev board we can use sot-223 lower current devices

[Mdtoday]

I believe that we could get away with disabling the boost reg at TX_OFF... and only blank for 20% of PRT from TX _OFF. I will work on implementing that in the FPGA. I will supply a blanking pulse to PMod J4 (probably pin 3).

Ok, that sounds good.