New Bipolar Boost TX and Front End

[KingJL]

... Is there a timing diagram of all the drive signals?

Not yet... but in the meantime timing can be determined by the LTSpice simulation.

I am thinking of trying this TX/pre-amp circuit but run the timing from a PIC32 instead of the FPGA.

I am not really sure that you can take advantage of the performance benefits with a PIC32, but I could be wrong. The reason I say this is I don't think the PIC can match the precise timing of the FPGA. The FPGA is accurate to a 100 MHz clock and all events happen exactly on a specific clock count as opposed to an instruction count or interrupt. With the PIC, if you are using interrupts, the nearest granularity is an instruction cycle, which means the event occurs with 1, 2, or four clock cycles depending on the instruction at the time of interrupt. To achieve the the accurate and flat current profile and a coil decay down to 2 mA in 4 usec, the timing has to be precise.

[waltr]

Thanks for the answer.

What I would use on the PIC32 is the Hardware OC (output compare) module. This can be setup to produce output high/low levels based on hardware timers. Resolution based on the 24MHz peripheral clock. I have used this for normal PI TX and RX Sample pulses.
Since this all runs in the hardware modules there is no software over head, jitter, etc.

I will get the LTSpice model running to study the timing requirements.

Thanks for all the posts about this project. Been lots to learn and enjoy.

Ok, just ran the sim and it looks like the PIC32 can generate the timing. Need more time to really study the circuit to be sure.

[Mdtoday]

The schematic and board layout is completed. I added test points (all accessible from the top side of PCB) for 5V, 20V, Vdd, REF, M5A&B source, M1 gate & M1 sorce, M3 gate & M3 source, M2 gate, M4, gate, m6 gate & M6 source, M7 gate & M7 source, and pre-amp out. I added an output line to J9 for the signal at the source of M5A&B. The TX current from the end of TX boost until TX off can be measured (voltage drop across R2, R3, R4, and R5) at this point. If we use the old IF board, we have to cut the trace from from J1-5 to PIO40 to prevent damaging the CMOD-A7 (we need a new I/F board).
Schematic:
[ATTACH=CONFIG]48760[/ATTACH]

Board top view:
[ATTACH=CONFIG]48759[/ATTACH]

Board bottom view:
[ATTACH=CONFIG]48758[/ATTACH]

Kicad arcive and gerbers:
[ATTACH=CONFIG]48761[/ATTACH]
[ATTACH=CONFIG]48763[/ATTACH]


@Mdtoday (and anyone else so inclined) would you put your eagle eye to the board layout when you get time. Again, none of this is time critical.

Thanks JL, looking great, I will sit down and go over the layout tonight, I have a few quiet hours to do so now.

[eclipse]

For me also will be easier to try and use PIC32MZ at first attempt maybe just for a proof of concept testing.
Timings are accurate-ish but I can't get them lower than 2.5uS precision so it's far from perfect.

[Mdtoday]

Thanks JL, looking great, I will sit down and go over the layout tonight, I have a few quiet hours to do so now.

@KingJL, the layout looks good. I will have another look over tomorrow to be sure but nothing stands out in error JL, nice work!

[waltr]

For me also will be easier to try and use PIC32MZ at first attempt maybe just for a proof of concept testing.
Timings are accurate-ish but I can't get them lower than 2.5uS precision so it's far from perfect.

If you use the Output Compare module then timing should be accurate to within the peripheral clock's timing. Do not try doing the timing in code. The PIC32MZ has 9 OC outputs so should be easy.
I am going to write some code for the MZ to doing the timing in the next week or so.

[KingJL]

Operation with correct timing

For me also will be easier to try and use PIC32MZ at first attempt maybe just for a proof of concept testing.
Timings are accurate-ish but I can't get them lower than 2.5uS precision so it's far from perfect.

For those interested in building this TX/pre-amp, I am posting these screen shots of different timings for the boost duration and the damp start timing to illustrate the effects of timing accuracy/granularity. My current design is using an FPGA running at 100 MHZ and has a timing granularity of 10 nsec. Clock jitter is < 10 psec. Any timing granularity greater than 10 nsec will have decreased performance. I put this forward not to advocate and preach the use of the FPGA, but to show the of timing accuracy and stability effects on the design. If you expend the effort and expense to build this circuit and use an alternate method to generate timing signals that cannot achieve this timing accuracy/granularity, you may be severely disappointed with the outcome. Again this is not to discourage experimentation,(which I actually encourage), but to make sure you are as informed as possible before you expend the $$ and time.

The timing change effects will be posted in separate 3 posts ( due to the attachment limitations... a picture is worth 1000 words ): (1) This post will show the coil currents and pre-amp output results from correct timings for the boost and damp signals. (2) A post showing the results of a 10 nsec timing change. (3) A post showing the results of a 2.5 usec granularity.

Coil Current (achieves constant current) with boost width set at 3.88 usec:


Coil current and pre-amp output with damp timing starting at 2.85 usec after TX off (coil current at start of damp = 1.003 mA):

[KingJL]

Timing effects with 10 nsec granularity

The timing change effects will be posted in separate 3 posts ( due to the attachment limitations... a picture is worth 1000 words ): ... (2) A post showing the results of a 10 nsec timing change...

A 10 nsec change to boost width has an effect of about 0.5 mA from optimal tha major effect at a granularity of 10 ns is the start of the damp.

Coil current and pre-amp out with damp set set to 2.84 usec (coil current at start of damp = 5.6 mA ... a change of 20 nsec brings the coil currebt at damp time to well over 10 mA ) :



Coil current and pre-amp out with damp set set to 2.86 usec (coil current at start of damp = -4.19 mA... note the pre-amp output swung sharply negative )

[waltr]

This is great KingJL and will be very helpful to evaluate other options to produce the timing.

Should we post in this thread info on using other devices to produce timing?

[KingJL]

Timing effects with 2.5 usec granularity

The timing change effects will be posted in separate 3 posts ( due to the attachment limitations... a picture is worth 1000 words )... (3) A post showing the results of a 2.5 usec granularity...

The effects using a granularity of 2.5 usec (even a granularity of 1 usec will have similar results).
Coil current with boost set to 2.5usec (damp timing left at optimal setting):


Coil current with boost set to 5usec (damp timing left at optimal setting):


Coil current and pre-amp output with damp timing starting at 2.5 usec (boost timing left at optimal setting) after TX off (coil current at start of damp = 173 mA ... note extended pre-amp coil decay time... also note that coil current flatness is affected slightly):


Coil current and pre-amp output with damp timing starting at 5 usec (boost timing left at optimal setting) after TX off (coil current oscilates from -39 to +40 mA until start of damp... note preamp output ):

[KingJL]

...Should we post in this thread info on using other devices to produce timing?

As long as it is pertinent to and peripheral to the subject of this thread, I see no problems... in fact welcomed. If it starts to overwhelm this thread and starts a different and unfocused objective, it may deserve a thread of it's own.

[KingJL]

New CMOD-A7_TXX/RX (ADuM driver Version) IF PCB

The new ADuM version of the TX/RX board required a new PCB to interface with the CMOD-A7 as the number of signal lines have changed. At the same time, I wanted to accommodate a future move to an LTC2378-20 ADC. Interfacing to a 20 bit ADC introduces some new challenges because of sensitivity to noise/interference. Interfacing with the LTC2378 introduces even more challenges because the LTC2378 and all support IC's are in MSOP packages. To reduce susceptibility to noise/interference and to insure short ground paths, a GND fill is applied to both the top and bottom boards and via stitching is applied with uniform spacing. Then the RX signal path to the ADC is "fenced" with gounding.
TX/RX IF board schematic:
TX(ADuM)_CMOD-A7 IF Board schematic.pdf

Top view:


Bottom view:



The LTC2378-20 and all support circuitry is optional as the current signal going to the CMOD-A7 XADC is still present. The FPGA HDL code will test if the LTC2378 is present and change the internal signalling and timing.

With the ADuM version of the TX/RX design, the PMOD sockets are no longer needed and have been removed. There is still the PMOD on the CMOD-A7 that is available if a PMOD is needed.

Over the next few weeks, the new I/F board schematic, PCB layout, and gerber files need to be vetted.verified. In support of that ongoing effort, I am posting the schematic, the kicad development file zip, the gerber files zip for the interface board, and the IF board BOM.

[Mdtoday]

The new ADuM version of the TX/RX board required a new PCB to interface with the CMOD-A7 as the number of signal lines have changed. At the same time, I wanted to accommodate a future move to an LTC2378-20 ADC. Interfacing to a 20 bit ADC introduces some new challenges because of sensitivity to noise/interference. Interfacing with the LTC2378 introduces even more challenges because the LTC2378 and all support IC's are in MSOP packages. To reduce susceptibility to noise/interference and to insure short ground paths, a GND fill is applied to both the top and bottom boards and via stitching is applied with uniform spacing. Then the RX signal path to the ADC is "fenced" with gounding.
TX/RX IF board schematic:
[ATTACH=CONFIG]48834[/ATTACH]

The LTC2378-20 and all support circuitry is optional as the current signal going to the CMOD-A7 XADC is still present. The FPGA HDL code will test if the LTC2378 is present and change the internal signalling and timing.

With the ADuM version of the TX/RX design, the PMOD sockets are no longer needed and have been removed. There is still the PMOD on the CMOD-A7 that is available if a PMOD is needed.

Over the next few weeks, the new I/F board schematic, PCB layout, and gerber files need to be vetted.verified. In support of that ongoing effort, I am posting the schematic, the kicad development file zip, the gerber files zip for the interface board, and the IF board BOM.

Excellent work JL! Looking really good. I will spend some time going over the circuits and layout during the next few days and report back.
Thanks for sharing

[Mdtoday]

@JL, just checking schematic against manufacturer data sheets and I couldn't locate the data sheet for an LT6302C device, is this meant to be LT6203C ?

https://www.analog.com/media/en/tech...s/620234fd.pdf

[Mdtoday]

@JL, I ran a schematic DRC and came up with the following errors...which are not critical as connections on PCB are correct .
To remove the errors I did the following;

Add label RX to pin 1 of J1

Re-assign pins of U2 ...
Pin 8 = input
Pin 1 = input
Pin 11 = output

Re-assign pin 6 of U4 to input

Remove no connect symbol from J2 Pin 8

I only mention this for clarity as my first round checking so far, has found no actual PCB to Schematic connection problems
Looks good! I will go over it again a couple of times to be sure.