New Bipolar Boost TX and Front End

[Mdtoday]

Looks great, I can't see anything else on the layout side that would cause issues.
Nice work on the interface board JL, I like the idea of the PMOD connectors.
Yes, I checked with PCBWAY and board tolerances appear to be ok.

I'll wait until you are happy with the layout and locked it down, then will order 5 of each

thanks for sharing

Cheers

Mdtoday

[KingJL]

I'll wait until you are happy with the layout and locked it down, then will order 5 of each...

I have rechecked pin connections and footprints against the datasheets for the EL7222, EL7202, DG333, DG418, THAT1512, and OPA828 to insure they are correct (I have been bitten by an alternate footprint before). I need to remake my mock-up of a EL7202 and my toroid pulse transformer to insure the polarity of the primary connections. That will take a couple of days.

[Mdtoday]

I have rechecked pin connections and footprints against the datasheets for the EL7222, EL7202, DG333, DG418, THAT1512, and OPA828 to insure they are correct (I have been bitten by an alternate footprint before). I need to remake my mock-up of a EL7202 and my toroid pulse transformer to insure the polarity of the primary connections. That will take a couple of days.

No Problems JL, in your time, thanks for the heads up, yes, I have been caught out on footprint check too, its not fun.
I have just ordered the Diligent 410-328-35T Development board and should see that in a week. $89 US turned out to be $156 AU with delivery but that is still good value for a development platform with the features this one has.
I generally have used these JTAG units but this board saves that hassle.


Oh, I noticed on the interface adaptor board, 3D viewer shows the PMOD connectors mirrored, they don't appear to be keyed so its not an issue but just noticed it.

Cheers

MDtoday

[KingJL]

Oh, I noticed on the interface adaptor board, 3D viewer shows the PMOD connectors mirrored, they don't appear to be keyed so its not an issue but just noticed it...

I mirrored the PMODs because the socket for the cmod-A7 is mirrored. When the assembly is oriented so that the Cmod-A7 is facing up, the pmods are up also. No, the pmod sockets are not keyed (as per the Digilent pmod interface specification). But I did place a "1" in the silk layer at the pin 1 end of the pmod sockets.

[Mdtoday]

I mirrored the PMODs because the socket for the cmod-A7 is mirrored. When the assembly is oriented so that the Cmod-A7 is facing up, the pmods are up also. No, the pmod sockets are not keyed (as per the Digilent pmod interface specification). But I did place a "1" in the silk layer at the pin 1 end of the pmod socket.

Ah, ok, thank you

[KingJL]

DSP processing

This weekend I developed some FPGA code to implement the timing for the TX/Rx. After getting the TX timing correct, I needed to decide on the suggested RX processing. It is envisioned that 3 samples will be taken and applied to 3 channels of integration filtering/processing. I wanted to use CIC filters, each followed by a compensation filter to flatten the pass band and sharpen the stop band. After some searching and some work to make it work correctly, I achieved a workable tool to generate coefficients for a compensation filter that will work with the Vivado FIR filter core. I designed the filter around the expected working parameters of the bipolar TX/RX. That being a operating range of 600 - 2000 pps with a 10% duty cycle. The filter can be operated within this range just by changing the decimation rate of the CIC (in steps of 200 pps). FIR coefficient sets will allow accommodating the 200pps span between the CIC decimation steps. Below is the integration flow for a prf of 2000pps (500 usec prt). I have confirmed that the Vivado core can support and generate this filter combination.

integration filter.pdf

[Altra]

Great progress JL. Once you work out the details it should give you lots of flexibility. Vivado looks interesting. Can you do a complete design using System Generator? I've only used Quartus and not familiar with Xilinx tools.

[waltr]

What is the delay through the filter?

What I am getting at is the time between a target passing under the coil and when there is a target indication (audio I hope).

Interesting project.

[KingJL]

What is the delay through the filter?

What I am getting at is the time between a target passing under the coil and when there is a target indication (audio I hope).

Interesting project.

Care must be taken on how to interpret the data... The target signal does not have to completely pass through the filter until there is a target indication. The target signal effects will start appearing after a few input samples. But to answer your question directly, the time for complete travel through the filter (where the level of output is absolute maximum for a given target) is (2 *number of sections * decimation rate * number taps of the FIR) samples. In the case of an operating rate 2000 pps, that would be 1920 samples. For an operating rate of 600 pps the total length is 320 samples. But that is for full integration to a signal maximum level of above the noise. The target will actually break the detection threshold much much earlier... within 10's of samples, much the same as an analog integrator. The main difference is the extremely low noise floor of the digital filter. In the CIC filter, an input sample starts to take affect after 4 + decimation rate samples (minimally at first but the effect quickly increases with each successive sample). With the FIR filter, the effect will be start to be seen after the first sample into the filter (again minimally at first, but quickly increases with each successive input).

[waltr]

Thank you for the explanation.
Makes sense.

[KingJL]

To be more precise from the generalized previous answer...

What is the delay through the filter?...

I have located the calculations for group delay through the filters. The group delay is basically the time from when a change is introduced into the filter until the effect is seen in the output assuming the change is within the passband of the filter. The group delay can be expressed in time or phase. These formulas calculate the group delay in time. For the CIC filter the group delay in seconds is T = 1/(((R-1)/2) * N) where N = filter order and R = rate change (decimation factor). For the FIR the group delay is T = (taps-1)/ (2 * Fs). For our 5th order CIC with a rate change of 10 and an input Fs of 2000, the delay is 44 ms. For our compensation fir with 16 taps and an input Fs of 200, the delay is 37 ms. So the combined group delay for the complete filter is 81 ms. Or another way to view it, is that after 162 samples at our operating frequency of 2000 pps, the integrated output will start appearing above the noise floor of the filter.

[KingJL]

FPGA TX Timing Module

Here is the output from the VHDL FPGA TX_Timing_Module. The simulator inputs to the module were: 100MHz clock, PRT=500, Sample1 = 8, Sample2 = 20, Sample3 = 40. The module takes the decimal PRT and Sample values (all are assumed to be usec), convert them to clock counts, calculate PW, and sets the clock count for each event in the TX/RX cycle. I have also attached the VHDL source statements as a text file. Anyone wishing the Vivado project files, PM me with your email address as the zip file is too large (currently 27 MB) to attach to a post.

TX Timing Sim.pdf

[eclipse]

You can upload it too Google Drive. Zip size is too high for most email providers as well.

[KingJL]

Vivado project files

You can upload it too Google Drive. Zip size is too high for most email providers as well.

Thank you!!

The Vivado project files are in a zip at this link.
https://drive.google.com/file/d/1A0Y...ew?usp=sharing

[green]

Could someone help could not open include file "spdt . sub" what do I need to do? Tried to open .sub file, don't know what to do with it. Why do I have to reenter all my pass words after clicking on a .sub file? Not a computer person.