New Bipolar Boost TX and Front End

[KingJL]

Yes, spotted those after running the sim, thanks for clarifying this.

If you don't spot something else, I'm getting ready to pull the trigger on sending the gerbers,for both boards, off for fabrication sometime in the next couple weeks.

[Mdtoday]

If you don't spot something else, I'm getting ready to pull the trigger on sending the gerbers, for both boards, off for fabrication sometime in the next couple weeks.

I had another look over it last night and could not find anything else, I think it looks OK to me.

If your gerbers have not changed since last posting, I will send off later today too, as I have some others to get manufactured.

I will get some extra done and send to you if you like at not cost of course, price is not a whole lot different for 5 or 10

cheers

Mdtoday

[KingJL]

... If your gerbers have not changed since last posting, I will send off later today too, as I have some others to get manufactured...

Just checked the gerbers... the dates on the gerbers were 2 days newer than the date on the zip files also the drill files for the TX were 2 days older than the gerber layers. So I just plotted the TX. The I/F board gerbers and drill files matched, but since they were newer than the zip, I re-zipped them. Might want to run a sanity check on them. Can I ask for 2 boards of each... I had promised someone a populated board.

[Mdtoday]

Just checked the gerbers... the dates on the gerbers were 2 days newer than the date on the zip files also the drill files for the TX were 2 days older than the gerber layers. So I just plotted the TX. The I/F board gerbers and drill files matched, but since they were newer than the zip, I re-zipped them. Might want to run a sanity check on them. Can I ask for 2 boards of each... I had promised someone a populated board.

Thanks JL, I'll do one last check and then if OK , will place an order.
I'll send 5 of each so you have some extras just in case.

Thanks for sharing the project.

Cheers

Mdtoday

[moorejl57]

And this also allows for higher pulse rates.



An H-bridge driver allows the use of a simple mono coil, but has higher parasitic C so it's tough to get super-fast speeds. I use H-bridge drivers where speed isn't critical.

What do you think about this en.DM00415791.pdf integrated driver/mosfet bridge for a bipolar setup? It seems reasonable in cost $6 and can be directly driven by a microcontroller 3.3V output.

[Mdtoday]

What do you think about this [ATTACH]46559[/ATTACH] integrated driver/mosfet bridge for a bipolar setup? It seems reasonable in cost $6 and can be directly driven by a microcontroller 3.3V output.

I have tried this unit and the Bootstrap circuit caused issues, so I put it aside a few months ago, might revisit it but not much time atm.

there is a project thread under STM32 somewhere in the Tech forum started awhile back but it went quiet.

My stm32 powered pi detector by GTdavid

cheers

Mdtoday

[KingJL]

... and the Bootstrap circuit caused issues, ...

That is the problem with all of the integrated H-bridge drivers that I have investigated... the capacitive bootstrap. I did see a driver series (I think Analog Devices) that was a fully integrated isolated H-bridge driver with in-chip pulse transformers that did not use the capacitive bootstrap, but have not got around to checking them out.

[moorejl57]

I have tried this unit and the Bootstrap circuit caused issues, so I put it aside a few months ago, might revisit it but not much time atm.

there is a project thread under STM32 somewhere in the Tech forum started awhile back but it went quiet.

My stm32 powered pi detector by GTdavid


cheers

Mdtoday

That is the problem with all of the integrated H-bridge drivers that I have investigated... the capacitive bootstrap. I did see a driver series (I think Analog Devices) that was a fully integrated isolated H-bridge driver with in-chip pulse transformers that did not use the capacitive bootstrap, but have not got around to checking them out.

Thanks for the info and for saving me some headaches. I was ready to give this a go.

[Mdtoday]

That is the problem with all of the integrated H-bridge drivers that I have investigated... the capacitive bootstrap. I did see a driver series (I think Analog Devices) that was a fully integrated isolated H-bridge driver with in-chip pulse transformers that did not use the capacitive bootstrap, but have not got around to checking them out.

Yes, this is what I have found

JL I have sent you a PM

cheers

Mdtoday

[KingJL]

... need to wrap my head around the XADC to acquire the samples...

I have been fighting the XADC for the last few days... finally have a configuration that functions correctly in a behavioral simulation in Vivado.

In ip catalog select the FPGA Features and Design -> XADC -> XADC Wizard, and then set up the tabs as follows:

Basic:
Interface Options = DRP, Timing Mode = Event Mode, Startup Channel Selection = Single Channel,
DRP Timing Options: DCLK =100 MHZ, ADC Conversion Rate = 1000, KSPS Aquisition Time = 4
AXI4STREAM= Enable AXI4Stream unchecked, Control/StatusPorts = nothing checked
Event Mode Trigger = convst in
Sim File Selection = Default, Analog Stimulus File = Design, Sim File location = ./, Waveform Type = CONSTANT

ADC Setup: Channel Averaging = None, Nothing else checked

Alarms: All unchecked

Single Channel: VAUXP4 VAUXN4, Channel Enable checked, Bipolar checked

I also have an uncluttered text (Design.txt) file to use instead of the generated design.txt file. You can change the values for the VAUXP[4] and VAUXN[4] and see the output of the ADC change.

New link to the Vivado project zip files dated 6-4-2019: https://drive.google.com/file/d/1t4Z...ew?usp=sharing

[Mdtoday]

I have been fighting the XADC for the last few days... finally have a configuration that functions correctly in a behavioral simulation in Vivado.

Thanks JL, I will have a play with this, I had a few problems with my Vivado install and my server firewall so not had much time to look at the design suite but all up and running now and Vivado does look quite good. I'll let you know how it goes

cheers

Mdtoday

[KingJL]

Major restructure of port interface

I have restructured the I/O interface for control of the TX by the embedded CPU. All control I/O with the module is now via a register array (currently 6 x 32 bit registers). The initial operating parameters are set by a set of generic's for the entity definition. This will allow the timing functions to be exercised without the inclusion of the embedded cpu or with minimal code for the embedded cpu.

Also the constraints file (CMOD-A7_master.xdc) has been modified to connect the output ports to the TX_IF_CMOD-A7 board J1.

The link to the new zip (Vivado_Bipolar_TX(6-13-2019).zip) file containing the Vivado project files is:
https://drive.google.com/file/d/1gEa...ew?usp=sharing

[Mdtoday]

I have restructured the I/O interface for control of the TX by the embedded CPU. All control I/O with the module is now via a register array (currently 6 x 32 bit registers). The initial operating parameters are set by a set of generic's for the entity definition. This will allow the timing functions to be exercised without the inclusion of the embedded cpu or with minimal code for the embedded cpu.

Also the constraints file (CMOD-A7_master.xdc) has been modified to connect the output ports to the TX_IF_CMOD-A7 board J1.

The link to the new zip (Vivado_Bipolar_TX(6-13-2019).zip) file containing the Vivado project files is:
https://drive.google.com/file/d/1gEa...ew?usp=sharing

Very nice work KingJL thanks for sharing

[KingJL]

Added 3 channel CIC sample integrator filter

New update for the Vivado project... Corrected a logic error that prevented sample 0 (2 usec after start of damp for purposes of tuning the damp timing) from ever being taken. Added the 4 stage, 3 channel CIC filter that filters samples 1, 2, & 3 and integrates the sample output from the XADC. I initially configured the CIC filter to operate in streaming mode with no success. I reconfigured the CIC to not use the streaming option (operates in block mode) and successfully instantiated the CIC sample filter. Added logic to read the samples as they are made available from the CIC and store them in the interface register set.

To run the Vivado simulator to exercise the module logic (after you have created a project folder for the project and unzipped the project file into that folder). Start Vivado, open the project and in the "Hierarchy" panel, expand "Simulation Sources"; right click "sim_1", select "RUN Simulation">"Run Behavior Simulation". After the simulation starts, in the Menu Bar, select "Run">"Restart". Then in the "Objects" panel, right click "CLK100_i", and select "Force Clock". In the "Force Clock" dialog box enter 0 into "Leading edge value:", enter 1 into "Trailing edge value:", enter 10ns into "Period:", and click "OK". Then in the Menu Bar select "Run">"Run for". In the "Run for" dialog enter the time that you wish to run. For viewing the timing signals, I usually run for 10 ms. To see the outputs for the CIC filter you need to run for more than 30 ms... I usually run for 50 ms as it allows for the filter to reach maximum output. After the "run for" time is reached (or while it is running) in the Logic Waveform panel Menu Bar click the "Go to Time 0" symbol, and the repeatedly click the "Zoom out" symbol until you have the time span that you want to see.

New link for zip ( Vivado_Bipolar_TX(6-15-2019.zip ) containing the updated project:
https://drive.google.com/file/d/1ZMR...ew?usp=sharing

[Mdtoday]

New update for the Vivado project...

New link for zip ( Vivado_Bipolar_TX(6-15-2019.zip ) containing the updated project:
https://drive.google.com/file/d/1ZMR...ew?usp=sharing

Thank you JL, I will try this tonight, It's looking very good.

I am about to start loading 2 sets of boards, I'll need to order the inter-board connector and I'm stilling waiting on the inductors to be delivered and jig up a 20v supply, so hopefully I can start checking power supply stages in a day or so at least.


Cheers

Mdtoday