New Bipolar Boost TX and Front End

[Mdtoday]

Made major moves forward this week. Developed a parameterized interface peripheral ip to control the Xilinx CIC ip...

After those 2 modules are added, we can focus on the code to tie everything all together.

Brilliant work JL, well done and thanks for sharing, looking really good!

I have ordered more boards which we should see in 2 or 3 days which I will load and test and send on to you.
Have yet to order the relay, I keep forgetting...

[KingJL]

... There only 2 hardware definitions left to integrate into the design. (1) A 2 channel (for samples 1 & 2) 16 tap finishing FIR filter that will both sharpen/narrow the passband and compensate for the unlinearity of the passband of the CIC filter processing...

To further illustrate the effects of the FIR finishing filter:
integration filter.pdf
The left side (CIC Filter)represents the bandpass of the Target_CIC filter in the Bipolar PI design. The right side (FIR Compensation Filter) shows the effects of the FIR finishing filter in the Bipolar PI design. The "Global" plot lines represent the resultant passband. In the design, the reason that this filter is referred to as "FIR finishing filter" is to not convey the inference that this filter contributes any ground "compensation" capability. Actually, we will be using the outputs of the "slow" (0.333 Hz - 0.005 Hz selectable in 10 steps) CIC filter to provide ground mineralization compensation capability and also SAT capability.

[Mdtoday]

To further illustrate the effects of the FIR finishing filter:
[ATTACH=CONFIG]47352[/ATTACH]
The left side (CIC Filter)represents the bandpass of the Target_CIC filter in the Bipolar PI design. The right side (FIR Compensation Filter) shows the effects of the FIR finishing filter in the Bipolar PI design. The "Global" plot lines represent the resultant passband. In the design, the reason that this filter is referred to as "FIR finishing filter" is to not convey the inference that this filter contributes any ground "compensation" capability. Actually, we will be using the outputs of the "slow" (0.333 Hz - 0.005 Hz selectable in 10 steps) CIC filter to provide ground mineralization compensation capability and also SAT capability.

Nice!, thanks for sharing

[KingJL]

One down... one to go

... There only 2 hardware definitions left to integrate into the design. (1) A 2 channel (for samples 1 & 2) 16 tap finishing FIR filter that will both sharpen/narrow the passband and compensate for the unlinearity of the passband of the CIC filter processing. (2) An audio peripheral that will provide a 1 bit DAC audio out signal based on the digital voltage signal.

After those 2 modules are added, we can focus on the code to tie everything all together ...

Implemented and integrated the FIR finishing filter peripheral. The FIR filter is implemented as a 1 channel FIR with 2 parallel paths for S1 and S2. Changed the debug printouts within the main() while(1) loop to print the notification of the interrupts and the corresponding filter output values for the filter interrupts.


Only one hardware peripheral definition left to design/integrate... the audio peripheral.


The current Bipolar PI design:


The change log:
Change Log.txt

The current project version is Vivado_Bipolar_PI(9-10-2019).zip

For those that are downloading and saving the archives, the previous version that was posted (Vivado_Bipolar_PI(10-6-2019).zip should be renamed Vivado_Bipolar_PI(9-6-2019).zip. I guess I was time traveling and did not realize it. I am surprised that I did not hear some flak about that. Please rename it so that that the actual latest version does not get confused.

[Mdtoday]

Implemented and integrated the FIR finishing filter peripheral. The FIR filter is implemented as a 1 channel FIR with 2 parallel paths for S1 and S2. Changed the debug printouts within the main() while(1) loop to print the notification of the interrupts and the corresponding filter output values for the filter interrupts.


Only one hardware peripheral definition left to design/integrate... the audio peripheral.
....
For those that are downloading and saving the archives, the previous version that was posted (Vivado_Bipolar_PI(10-6-2019).zip should be renamed Vivado_Bipolar_PI(9-6-2019).zip. I guess I was time traveling and did not realize it. I am surprised that I did not hear some flak about that. Please rename it so that that the actual latest version does not get confused.

Excellent work as usual JL!

Looking great. Must admit I didn't notice the date on the last Zip file..

I still have not received the Power and Probe switch PCB's , JLPCB have been a bit slow this time round, normally I have them in 5 days from order date but I had to contact them 3 times as they had completed only 2 boards, they hadn't started the probe switch until early yesterday, now they are just sitting in waiting for pick up. I mean its still a whole lot quicker than by-gone years when we would have to pay a small fortune for tooling and wait 6-12 weeks but I was hoping to have them for this weekend to load...never mind, these thing s happen. I suspect because the Mid-Autumn holidays in China start on the 13th and last for 3 days, we may not see them for another week. I could only purchase 2 Kemet relays from LCSC too, so looking for another supplier atm.

[KingJL]

Missing sample 0

... The current project version is Vivado_Bipolar_PI(9-10-2019).zip ...

If you have run the application, you will notice that the S0 sample is always "0". I had checked the read register code in the application, the read register VHDL in the hardware design, and the RX XADC read code... and could find nothing. I changed the code to provide a "valid" bit in the high byte of the word provided to the register manager. Still no entry into register_set(4), which is the S0 slot. It was as if S0 was never requested. A recheck of the VHDL revealed nothing... a simulation run of the TX-RX module showed all samples clearly requested and stored in the register set. But in actual operation still no S0 (register_set(4). Finally found the culprit... the integer "range" of a local variable "local_cntr" was set to "0 to 150" and the count value being tested for was 200. Changed the range "0 to 500" and re-senthesized, implemented, generated the bitstream, and executed the application... now we have S0! The simulator synthesizer does not trim integer signals/variables to implement the range limitation. This fix will be included in the next posted version.

[Mdtoday]

If you have run the application, you will notice that the S0 sample is always "0".

... now we have S0! The simulator synthesizer does not trim integer signals/variables to implement the range limitation. This fix will be included in the next posted version.

Thank you for the update JL, l have not run the latest application yet, was planning to do that over the weekend.
This is a large and well thought out and logically ordered project you have put together.

Received parts from LCSC today, mainly JST connector sets and relays. JLPCB have finally dispatched the power supply and 2 probe PCBs so will see them Monday.
Although I have only 2 relays, all other parts have arrived including a PMOD style connector kit you put me onto a few week back, so next week I will be concentrating on loading 2 or 3 sets of those boards for testing.
I will PM you when they are completed, tested and ready to send. Will also 3D print more internal enclosures and forward on some extra blank boards.

cheers

Mdtoday

[KingJL]

...l have not run the latest application yet, was planning to do that over the weekend...

Also, on the current version, the output of the target CIC filter has about a 72 db gain. In the next version the Target CIC will have a gain of 1. The RX signal form the XADC will be 24db above the actual measured value(left shifted 4 bits). This does not actually increase the gain, but does give a better realized target resolution granularity when averaged through the CIC filter. If you wish, I can post this version as there will not be much change in the next 2 weeks... I have some personal commitments that I must fulfill. I can wrap it up in an archive and post it later today.

[KingJL]

Also, on the current version, the output of the target CIC filter has about a 72 db gain. In the next version the Target CIC will have a gain of 1. The RX signal form the XADC will be 24db above the actual measured value(left shifted 4 bits). This does not actually increase the gain, but does give a better realized target resolution granularity when averaged through the CIC filter. If you wish, I can post this version as there will not be much change in the next 2 weeks... I have some personal commitments that I must fulfill. I can wrap it up in an archive and post it later today.

New archive that contains fixes for the items listed above is Vivado_Bipolar_PI(9-12-2019).zip

Change log:
Change Log.txt

[KingJL]

... so next week I will be concentrating on loading 2 or 3 sets of those boards for testing...

May I make a suggestion? Do not mount the 4 MOSFETs until the gate voltages can be verified... the toroids may need tweaking. On the toroids that I have, I remove one winding. The remaining coil has 14 turns of wire and i compress and tighten these windings on one half of the core. Then I wind 4 turns of 22AWG or 24AWG tightly in the center of the remaining half with the direction of the wind being the same as the remaining winding. All of this results 15+ volt gate drive. Five turns results about 12-13V .

[Mdtoday]

Also, on the current version, the output of the target CIC filter has about a 72 db gain. In the next version the Target CIC will have a gain of 1. The RX signal form the XADC will be 24db above the actual measured value(left shifted 4 bits). This does not actually increase the gain, but does give a better realized target resolution granularity when averaged through the CIC filter. If you wish, I can post this version as there will not be much change in the next 2 weeks... I have some personal commitments that I must fulfill. I can wrap it up in an archive and post it later today.

Excellent, yes that would be good thank you

[Mdtoday]

May I make a suggestion? Do not mount the 4 MOSFETs until the gate voltages can be verified... the toroids may need tweaking. On the toroids that I have, I remove one winding. The remaining coil has 14 turns of wire and i compress and tighten these windings on one half of the core. Then I wind 4 turns of 22AWG or 24AWG tightly in the center of the remaining half with the direction of the wind being the same as the remaining winding. All of this results 15+ volt gate drive. Five turns results about 12-13V .

Ok, yes that is a good idea to verify the gate drive, thanks for the info on the windings

[Mdtoday]

While waiting for Power boards to arrive, I have returned to the enclosure design and modified the mountings to suit the new board.

There is now access to adjustment pots and the 3 connectors (power outputs, power switch and probe)



Once the positions are verified with all the actual parts / board/ assemblies to be fitted, I will then de-construct the enclosure design, reduce the design weight and slice into all the printable sections.

The main enclosure can be printed in 2 halves at the same time but the print time is too extreme for me. I like to keep each print run time to no more than 24 hours so I can keep an eye on things and maintain the printer in between runs.

[Mdtoday]

Progress on the hardware.

Rev 2.00 Power and Probe switch boards arrived this morning, so I will load them later today and test.


Started the first full size draft print of the main enclosure 11hrs into a 15hr print.
I'll start the other side tonight

[KingJL]

Progress on the hardware.

Rev 2.00 Power and Probe switch boards arrived this morning, so I will load them later today and test.
[ATTACH]47460[/ATTACH]

Started the first full size draft print of the main enclosure [ATTACH]47461[/ATTACH] 11hrs into a 15hr print.
I'll start the other side tonight

Looking great!!