TineFPGA-GOLD Metal detector

[MartyJ1963]

Great Job SaltyDog!!,,,,Following this thread for sure! Regards,Marty.

[fb_bf]

I would like to help on this project

I'm new to this forum, so bear with me for awhile. I joined this forum because I wanted to try something very much like this. I have spent the last two weeks reading Carl's book on metal detectors, and going over many of the threads in this forum. A couple of years ago I saw how PI detectors worked and wondered if the receive signal could be digitized and then processed, couldn't the detector get all sorts of extra information from the signal. I am retired and interested in working on such a project. I have 10 or more years of experience with digital servo systems and sampled systems. I have a basic analog understanding and Ok to good coding skills. I recently bought a micro from ST which has two 5Msps 12 bit ADC's that can be interleaved if necessary with this project in mind. After doing all this research I was just about to start contacting members who could help me with getting a good analog PI front end. I don't want to reinvent the wheel. Since I'm interested in gold detection, (small gold since I live in Colorado) I wanted something with a fast front end and coil. I don't know anything about FPGA's, but I'm willing to help you on this if you're interested. I'm retired with no ambitions about getting rich from development efforts. I do own a Rigol DS1054 scope, so I can do my own analog debug. I hope I can help.

[dbanner]

Some arrows were pointing in the wrong direction.

[Skippy]

DB : two of the filters are IIR ( Infinite Impulse Response) not FIR.

Could the (1)'s and (2)'s simply be joined with lines ?

[dbanner]

Yes, I used the upside down photo to redraw the diagram. On a small android phone it is a little hard to see.

I will make the corrections. Also I put first ADC instead of fast ADC.

I think all is well now.

[dbanner]

Could the (1)'s and (2)'s simply be joined with lines ?

What do you mean, please explain.

[SaltyDog]

Yes, I used the upside down photo to redraw the diagram. On a small android phone it is a little hard to see.

I will make the corrections. Also I put first ADC instead of fast ADC.

I think all is well now.

Thanks for doing that, looks good, the only think I would change is to mark the Red block as CPU rather than "Logic", as it is a micro, not just FPGA logic blocks ..

Thanks again.

[SaltyDog]

I'm new to this forum, so bear with me for awhile. I joined this forum because I wanted to try something very much like this. I have spent the last two weeks reading Carl's book on metal detectors, and going over many of the threads in this forum. A couple of years ago I saw how PI detectors worked and wondered if the receive signal could be digitized and then processed, couldn't the detector get all sorts of extra information from the signal. I am retired and interested in working on such a project. I have 10 or more years of experience with digital servo systems and sampled systems. I have a basic analog understanding and Ok to good coding skills. I recently bought a micro from ST which has two 5Msps 12 bit ADC's that can be interleaved if necessary with this project in mind. After doing all this research I was just about to start contacting members who could help me with getting a good analog PI front end. I don't want to reinvent the wheel. Since I'm interested in gold detection, (small gold since I live in Colorado) I wanted something with a fast front end and coil. I don't know anything about FPGA's, but I'm willing to help you on this if you're interested. I'm retired with no ambitions about getting rich from development efforts. I do own a Rigol DS1054 scope, so I can do my own analog debug. I hope I can help.

Hi,

Thanks for the offer, may take you up on it.

I am also "old in the tooth" regarding electronics ... spend some 50 yrs in the field. I have found that for this application high speed DSP functionality is required, which means that a simple
micro is not up to the task ... we are looking at slopes of only several us in length, which needs to be processed with ns resolution, only a FPGA can do that.

Currently I am clocking the front end at 48Mhz (~20ns) but I can clock it at 192Mhz if required ..

Since I am happy with the discrimination side, I need help with the op-amp design. I like the MPP op-amp with it's double stage, but it has issues with saturation and speed ... I will replace the op-amp with a faster one in the meantime (>50v/us slew rate), but it does need a re-design in order to pass a slope that may only be 5us, with a fast coil. I have built a spider weave coil that has a slope of only 2us, but the current op-amp (NE5532) cannot handle it

Any suggestions/designs for the op-amp welcome ..

[dbanner]

CPU

[SaltyDog]

A better pre-amp design might be something like this one .. from the MPP thread.
.. or maybe just take the diode idea and apply it the the original MPP op-amp circuit, and change out the NE5532 for a faster one ..

..the diodes would help solve the saturation issues ..

[waltr]

Other op-amps may help and two stage to split the gain does help.
Check the MAX412/410 & LTC6230.

The first op-amp will set the Noise figure so that one could be the low noise op-amp with moderate gain then a fast recovering op-amp with more gain.

[SaltyDog]

Just made a discovery. The op-amp was not overshooting, I just needed more damping on my coil, it is now critically damped.

Result is my gold ring sensitivity has increased to 200mm ... which is a great start ..

However, I see the output signal from the MPP with respect to -5v (my FPGA GND) only varies from 2v..5v, so I am going to have to level shift that to the 0..3v3 that my ADC expects ..
Will work on that ..

[waltr]

I have found that for this application high speed DSP functionality is required, which means that a simple
micro is not up to the task ... we are looking at slopes of only several us in length, which needs to be processed with ns resolution, only a FPGA can do that.

Currently I am clocking the front end at 48Mhz (~20ns) but I can clock it at 192Mhz if required ..

The only part of your block diagram that needs to be FAST is the ADC. Once the decay curve is digitized then the processing can take a while and does not even need to be finished before the next pulse.

I have been playing with PIC32MX (50MHz) and a PIC32MZ EF (200MHz with FPU).
With these part of the 'trick' is having the hardware do the up-front work- OC modules to generate TX pulse theh triggers Timer to run ADC and DMA to move data to memory. Processing can be running while the next TX pulse & ADC measurements happen.
ADC sampling time resolution is done with a Hardware timer so post processing this data does not lose time resolution.

We also do not need updates to LEDs or audio at the TX pulse rate so I have summed 8 to 32 TX pulse/RX curve cycles before processing and output to user. Summing decreases Noise and adds ADC resolution by sqrt(N). Now there is a lot of time to process.

[SaltyDog]

Other op-amps may help and two stage to split the gain does help.
Check the MAX412/410 & LTC6230.

The first op-amp will set the Noise figure so that one could be the low noise op-amp with moderate gain then a fast recovering op-amp with more gain.

Thanks. The MAX412 would not be fast enough regarding slew rate, I think we need fast slew rate amps in both locations, the LTC6230 would be good ..

[fb_bf]

I agree with waltr, the fast part of this needs to be the ADC. That is why I thought this micro would be good. In theory it can sample at 10 times per usec!. I haven't tried it yet, but I'm assuming that it's DMA memory transfer will allow me to grab 100 usecs of data and store it in a 1000 array location. Then the processing can be done before the next pulse. This micro has a FPU and DSP built in. I have run a an IRR filter on a texas instruments Tiva C series mico using the FPU. I'll start looking into trying this approach to see if I can get that part to work. That is needed and independent of what you are doing.

Frank