I have mostly completed my design work on my analog metal detector which is named AGD23-2 but will be updated to AGD23-3 for the final version. The AGD standing for Alaska Gold Detector. The goal of this project was to design an analog detector using modern components as my performance standard to compare later versions that could contain some form of digital signal processing. My requirement for this project was that it would not need a menu along with its required digital display. All control would be by rotary controls and toggle switches whose position could be determined by a simple glance at the control panel. Audio out alert tone output to be a low distortion sine wave that idle at about 400hz, be able to detect very small gold, and have the ability to drive a internal speaker.
The timing logic in the present design calls for the high speed version of the old 555 timer, the ICM7556ISD+. What I'm considering is to potentially replace the timing the c-mos logic with some sort of processor or even a FPGA that can accept rotary encoder inputs instead of the three linear controls that connect to the TMG connector at the top right of the diagram posted for an potential future upgrade.
The logic comes out with four time slots, TS-0 , TS-1, TS-2, TS-3 and TS-4. TS-2 being the total time of TS-0 and TS-1. Time slots TS-3 and TS-4 are not used in the current design and set the remaining time.
DecayEnd goes positive which comes from the TX board and provides a pulse only on the first set point crossing and activates analog gating.
JP1 on the DecayEnd input is provided so RX board testing of the RX board can be done without having a coil connected and a 100 or 1000 to one attenuation and signal generator is connected to the RX input.
The question I have If I were to replace the cmos logic with some other method what would be the suggested way. This is not a lot of logic and I think a rotary encoder is likely about the same costs as linear potentiometer. Its been a long time since I have done of that kind of work. I have a AVR starter kit but it may be out of date.
The timing logic in the present design calls for the high speed version of the old 555 timer, the ICM7556ISD+. What I'm considering is to potentially replace the timing the c-mos logic with some sort of processor or even a FPGA that can accept rotary encoder inputs instead of the three linear controls that connect to the TMG connector at the top right of the diagram posted for an potential future upgrade.
The logic comes out with four time slots, TS-0 , TS-1, TS-2, TS-3 and TS-4. TS-2 being the total time of TS-0 and TS-1. Time slots TS-3 and TS-4 are not used in the current design and set the remaining time.
DecayEnd goes positive which comes from the TX board and provides a pulse only on the first set point crossing and activates analog gating.
JP1 on the DecayEnd input is provided so RX board testing of the RX board can be done without having a coil connected and a 100 or 1000 to one attenuation and signal generator is connected to the RX input.
The question I have If I were to replace the cmos logic with some other method what would be the suggested way. This is not a lot of logic and I think a rotary encoder is likely about the same costs as linear potentiometer. Its been a long time since I have done of that kind of work. I have a AVR starter kit but it may be out of date.
Comment