Is IRF9640 the best choice for a high-side switching topology?

[Carl-NC]

This thread is about what is the best PMOS for the more traditional high-side PI TX. I've presented the IRF9640 and the IXTP10P50P as my own suggestions and you've presented an alternative configuration that could operate in the same layout as PMOS. But with NMOS. I don't understand these replies about just using NMOS.

You can't use an NMOS in your situation without substantial redesign. Forget about it. Let's go back to the original question:

Hi guys,
as the title asks, for a PI that uses a high-side configuration for the coil is there a better choice (generally speaking) P-channel FET than the IRF9640? I'm in the process of redesigning an old metal detector for someone and one of the limiting factors is that the system needs to be compatible with already established coils. The coils themselves are separated with the Tx being 80uH and the Rx being 2000mH . My Tx pulse width is 60us with a period of 500us. I'd like to increase pulse width further to "push" more current into the coil but the IRF9640 gets substantially hotter if the pulse width is increased from this point (currently stands at about 50C at ambient with a big TO-220 heatsink). Is there a P-channel part that has lower RDson than 0.5 Ohm with similar or better avalanching specs?

Let's look at the numbers; I'll assume the total TX resistance is 1Ω:

Coil tau = L/R = 40uH/1Ω = 40us

Peak current at turn-off is



Energy in the coil is



Power dissipated is



Now let's double the pulse width to 120us:







So doubling the pulse width more than doubles the power. Most of this gets dissipated in the PMOS because of avalanching. You can use a higher breakdown PMOS to reduce the PMOS power but the energy still needs to be dissipated so now the damping R and clamp R will get hotter. And battery life is halved.

You have two other variables to try. One is to reduce the pulse rate. Halving the rate from 2kHz to 1kHz will get you back to about the same overall power, but this reduces the integrator averaging by half, so you may lose sensitivity overall. The other is to add some series resistance to the coil. This seems counterproductive but it helps flat-top the coil current which can improve depth on higher conductors. For example, if you add 1Ω and use a 120us pulse width the peak current s now 5.7A, slightly less than before. But the current slope at turn-off is improved from 71mA/us to 7.5mA/us. Whether this actually helps depends on the target.

Which brings up the question: what are you trying to accomplish?

[CrizzyD]

Which brings up the question: what are you trying to accomplish?

How can I reduce heat dissipation while maintaining sensitivity, while using the same (or similar) TX configuration?

The answer so far has been to source a PMOS with higher avalanche ratings. I am looking at going from IRF9640 to IXTP10P50P. Thats a difference of 200V to 500V breakdown.

Total back EMF generated in the coil is approximately 800V so The IXTP10P50P still avalanches but at a much higher voltage and so generates less heat. This means that I could increase the pulse width slightly to maintain the same thermal dissipation but with increased sensitivity. This is still better than what i currently have, but not ideal. The FET is operating at approximately 70°C at maximum pulse width of 80us with period of 500us.

The TX coil and RX circuit are fixed and cannot be changed.

I have tried adding series resistance to the coil to limit avalanche to 500V and this has reduced sensitivity, so I may as well just reduce the pulse width.

[Altra]

You can use a snubber circuit to limit the flyback voltage without degrading your signal.

Here are ones that I use. The capacitor should be 47uf or greater and the diodes need to have a fast recovery like UF4004 -UF4007's or similar

[CrizzyD]

Carl-NC Why wouldn't moodz suggestion be an option? The fundamentals seem reasonably sound for the TX (although I wouldn't be able to implement due to the aforementioned fixed receive circuit design, which expects a recovery curve below 0V, as is expected with a high side PMOS PI design). By the way, thank you very much for the help in these threads, I've bought your book and suggested it to my University. I guess I'd have to thank ElectroBoom too.

[Carl-NC]

So is the goal to reduce heat while maintaining the same performance, or to increase performance while maintaining the same heat?

The bottom line is, you can reduce the PMOS heat with a higher voltage PMOS, but that will only move the heat somewhere else, probably the damping resistor. The energy in the coil has to go somewhere.

Why wouldn't moodz suggestion be an option?

Exactly as you say, it creates an inverted target signal that won't work for the remainder of the circuit.

[kt315]

I am looking at going from IRF9640 to IXTP10P50P.

you again do not see differences. irf9640 has 0.5 Ohm rds while ixpt has 1 Ohm rds. losses on heat grows in 2 times.

[CrizzyD]

So is the goal to reduce heat while maintaining the same performance, or to increase performance while maintaining the same heat?

To reduce heat while maintaining the same performance. As I've mentioned I've come to realise that there is no cure-all for this particular design so I will stick with what I have for now until I redesign with an NMOS.

but that will only move the heat somewhere else, probably the damping resistor

That's fine, as long as the resistor is rated appropriately.. Would be great to be able to dissipate the heat over the coil rather than a component but I'm not sure how to even start with that one.

[Carl-NC]

you again do not see differences. irf9640 has 0.5 Ohm rds while ixpt has 1 Ohm rds. losses on heat grows in 2 times.

Rds only accounts for a small fraction of the overall power dissipation, so doubling Rds makes less difference in power than you think. It will, however, reduce the peak current and could slightly reduce depth.

To reduce heat while maintaining the same performance. As I've mentioned I've come to realise that there is no cure-all for this particular design so I will stick with what I have for now until I redesign with an NMOS.

A problem with this design is that the TX inductance is really low. Most PI designs use 4x the inductance (2x the turns) which is a more optimal balance in power and speed. The reason for using a low inductance coil is when you want raw speed, such as a 1 or 2 us sample delay, and the reason for doing that is to detect ultra-tiny targets. So before a redesign, I would ask, what is the intended use?

That's fine, as long as the resistor is rated appropriately.. Would be great to be able to dissipate the heat over the coil rather than a component but I'm not sure how to even start with that one.

The coil can only dissipate heat during the turn-on time, you cannot dissipate the flyback energy in the coil. The flyback heat is typically 90% of the total heat.