Eric Foster's CS4 uses a CD4017 to divide the input signal by ten. With three clocks
used to excite the TX coil, that leaves seven clock (time slots). Primary and
secondary samples are spread among the remaining seven slots.
By adding a flip flop and an analog switch you can force the CD4017 count to go as
high as eighteen (but the count must be an even number, divisible by two). By adding
an inverter it is possible to count to twenty, but that is not where I am going
because it gets hairy when you try to implement a twenty count in the scheme I
describe below.
I am attempting a design with two channels working at the same time. Channel 1 (CH1)
counts to 18 then resets, and CH2 counts to 16 then resets. Using two different diode
OR gates allows for having each channel to excite the transmitter for differing
numbers of clocks.
I have figured out a way to interleave the two channels so that either CH1 and CH2 can
output between one and nine cycles (inclusive) before the other channel takes over.
That means, you can interleave the transmit signals with 1:1, 5:3, 8:5, 3:5, 9:1 ratios
(and etc., you get the picture). Or, use either channel alone. The interleave ratio in my
simulation screen-shot picture is 1:4.
What I am attempting to do is replicate the TDI ground cancelling scheme twice over,
with each channel timed differently so that the detection holes in the two channels
will not overlap.
I do not have the math skills to analyze my circuit to determine where either
detection hole will be, and that is why I am here.
Can anybody help me with the math, or logic (or whatever) to try and ascertain that
the two detection holes will not overlap? My hope is that if a good target is missed by one
channel, it might still be detected by the other channel.
I almost hate to divulge my idea because some other rascal might be able to bring this
beast to fruition before I can (I'm like a slow leak) - but here it is. Each channel has separate drive circuitry
and different values of series resistance can be used in each channel to limit the two coils'
maximum current. You could (or should) have different coil tc's for each channel.
You could use a monocoil, no problem. One possibility for this design is to drop
the TDI ground cancelling scheme, instead, using a dual or center-tapped coil and
transmitting each channel with opposite polarity. For that matter, a OoO coil
might be employed, but that discussion will be left for another day.
As I understand the TDI's ground cancelling scheme (thank you Carl, for the info)
ground cancelling is accomplished by taking four samples, TGT, GB, EF1, EF2. The
receiver's post amplifiers are arranged to implement the following formula:
A(TGT-EF1)-B(GB-EF2), where A and B represent differing levels of gain (and B>A).
Now, again, how does the timing get analyzed to determine where detection holes will fall?
I suppose the math is over my head so that I may just as well rely on trial and error
(which I can be very good at) but I need to ask, just the same. Calculus strains my brain but
we all need to broaden our horizons, right? I'm still trying to "proof" my circuit before committing
it to PCB but most of the layout is done (just hoping I won't feel the need to do any extensive rework).
Thanks for any and all replies.
used to excite the TX coil, that leaves seven clock (time slots). Primary and
secondary samples are spread among the remaining seven slots.
By adding a flip flop and an analog switch you can force the CD4017 count to go as
high as eighteen (but the count must be an even number, divisible by two). By adding
an inverter it is possible to count to twenty, but that is not where I am going
because it gets hairy when you try to implement a twenty count in the scheme I
describe below.
I am attempting a design with two channels working at the same time. Channel 1 (CH1)
counts to 18 then resets, and CH2 counts to 16 then resets. Using two different diode
OR gates allows for having each channel to excite the transmitter for differing
numbers of clocks.
I have figured out a way to interleave the two channels so that either CH1 and CH2 can
output between one and nine cycles (inclusive) before the other channel takes over.
That means, you can interleave the transmit signals with 1:1, 5:3, 8:5, 3:5, 9:1 ratios
(and etc., you get the picture). Or, use either channel alone. The interleave ratio in my
simulation screen-shot picture is 1:4.
What I am attempting to do is replicate the TDI ground cancelling scheme twice over,
with each channel timed differently so that the detection holes in the two channels
will not overlap.
I do not have the math skills to analyze my circuit to determine where either
detection hole will be, and that is why I am here.
Can anybody help me with the math, or logic (or whatever) to try and ascertain that
the two detection holes will not overlap? My hope is that if a good target is missed by one
channel, it might still be detected by the other channel.
I almost hate to divulge my idea because some other rascal might be able to bring this
beast to fruition before I can (I'm like a slow leak) - but here it is. Each channel has separate drive circuitry
and different values of series resistance can be used in each channel to limit the two coils'
maximum current. You could (or should) have different coil tc's for each channel.
You could use a monocoil, no problem. One possibility for this design is to drop
the TDI ground cancelling scheme, instead, using a dual or center-tapped coil and
transmitting each channel with opposite polarity. For that matter, a OoO coil
might be employed, but that discussion will be left for another day.
As I understand the TDI's ground cancelling scheme (thank you Carl, for the info)
ground cancelling is accomplished by taking four samples, TGT, GB, EF1, EF2. The
receiver's post amplifiers are arranged to implement the following formula:
A(TGT-EF1)-B(GB-EF2), where A and B represent differing levels of gain (and B>A).
Now, again, how does the timing get analyzed to determine where detection holes will fall?
I suppose the math is over my head so that I may just as well rely on trial and error
(which I can be very good at) but I need to ask, just the same. Calculus strains my brain but
we all need to broaden our horizons, right? I'm still trying to "proof" my circuit before committing
it to PCB but most of the layout is done (just hoping I won't feel the need to do any extensive rework).
Thanks for any and all replies.
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