High Resolution ADC

[KingJL]

For a long time, I have been searching for an affordable, high resolution ADC to support some of my metal detector experimental projects that are FPGA/uPC based. I wish to sample with a preamp gain of 64 or less. Twenty four bits with a sample rate of at least 200 ksps would be ideal, but a minimum of 18 bits could suffice. There are some audio codec ADC's that could fit the requirements, but they all have built in HPFs that preclude their use in my applications and most are power hogs. Alas the search has been less than successful.


So… I designed my own! It uses the TI ADS8881 18 bit @ 1Msps. I designed the board to be pmod compatible. All components are SMD and the board dimensions are 1.95” x 0.8”. I sent off the gerbers and obtained the boards. The board house does 10 5mm x 5mm boards for $15, so I now have 20 (2 per 5mm x 5mm board). I have enough of the components to populate 3 boards (thanks to TI's free samples).


In this design, the ADS8881 is configured for 3 wire with or without interrupt SPI operation (see the TI ADS8881 Data Sheet).


I have moved to Kicad for all my board design work. All of the Kicad files are in the zip file included with this post. Also posting the schematic and board layout as pdf's.

[Skippy]

Ten 50mm x 50mm boards, I presume?

[KingJL]

Ten 50mm x 50mm boards, I presume?

You presume correctly!!

[fixstuff]

Is the circuit configured for single ended inputs? With differential inputs, is pin 6 supposed to be connected to gnd, or a -Vs? I'm just asking..

[rickb]

If only the HPFs in modern inexpensive codecs found in sound cards could be disabled. Sigh.

Rick

[KingJL]

Is the circuit configured for single ended inputs? With differential inputs, is pin 6 supposed to be connected to gnd, or a -Vs? I'm just asking..

It is configured for single ended input. The positve input or negative input pin can be selected depending on desired polarity to the ADC. The unused input pin is jumpered to GND via a shunt on the pin header pins.

[KingJL]

Populated board (except for the input pin header ).

[KingJL]

Test results

Well, I finally stepped up and procured my Spartan 6 FPGA development system and decided to test the pmod digital interface. I had previously tested the analog circuits and found everything working properly. Not so with the digital interface... there were 3 problems. 1. The pmod interface connector, P1, was inverted from what is required. Easy fix... turn the board over. 2. The 47 ohm resistors R10, R11, R12 were distorting the clocking and data signals at the required clocking rate. Easy fix... replaced the 47 ohm resistors with 0 ohm resistors. 3. The 22k pull-up R13 is connected to CS/CONVST instead of MISO/DOUT as required for interrupt operation. This one involved a board hack... stood the 22k on end on the 3.3V pad and connecetd a wire from the to of the 22k to a pad on R11. Now everything works. I tried clocking the ADC interface a 50 MHz... no luck through a PMOD socket. Backed the clocking rate to 25 MHz and everything worked OK with board plugged cirectly into the PMOD socket. Using a 6" cable to connect to the PMOD socket, required a slower clock... backed it down to 16.666 MHz and everything was stable.

Overall, I am quite happy with the results... I now have a working 18 bit ADC to use in my digital MD project ( http://www.geotech1.com/forums/showt...ed-PI-Detector ).

I am posting a corrected schematic... I will post updated kicad files when I get around to changing the board layout to correct P1 issue and pull=up issue.

ads8881_pmod_5v_schematic.pdf

[Taktyk]

Hi KingJL,

The reference voltage is 4.5V. What you value reading from 18-bit ADC - digital output code (Hex or DEC. For OV and 4,5V?

Regards

[KingJL]

Hi KingJL,

The reference voltage is 4.5V. What you value reading from 18-bit ADC - digital output code (Hex or DEC. For OV and 4,5V?

Regards

The input range to the board is single ended 4.5v to -4.5v. The THS4521 configuration converts this to a differential 0 to 4.5 with a common mode voltage of 2.25v. The ouiput for 4.5V input is 131071, 0V = 0, -4.5V = -131072. It is hard to properly represent a negative 18 bit number in hex the, 20 bit hex equivalent is 1FFFF, 0, E0000.

[KingJL]

Updated kicad and gerber files

I updated the kicad file, board layout, and gerbers. All are bundled in the following zip. The gerbers are in the folder named production.

[Davor]

This looks good.

[KingJL]

This looks good.

Thanks Davor

I am posting the VHDL code that synthesizes correctly with Xilinx ISE and was used to test the operation of the ADS8881 pmod board. I am using Xilinx ISE WebPACK for FPGA code development for the Spartan 6 FPGA. I have extensively commented the code so that the functionality should be able to be understood, making easier to develop an interface in other technologies (e.g. programming a uPC). The ADS8881.vhd is the driver code that controls the ADC. The ADS8881_test.vhd is the top level used to exercise/test the ADS8881.vhd code.