FPGA based PI Detector

[KingJL]

I am in the process of implementing an FPGA based PI metal detector. I am using the Xilinx Spartan 6 LX25 FPGA as the basis for this project.
http://www.xess.com/shop/product/xula2-lx25/
http://www.xess.com/shop/product/stickit-mb/
I chose the FPGA route vs the micro-processor (uPC) route due to the demanding DSP requirements and timing requirements. In the uPC route, everything happens sequentially. Even if using interrupt driven processes, everything is sequential and all processes have to share the same overall time limitation (usually the PRT of the TX). In FPGA implementation, each process has it’s own resources and executes concurrently with all other processes. Example: The TX pulse generation and sample request process does one thing; generate accurate timing of TX and sample requests… nothing else. It does not have to share time or resources with any of the DSP processes, threshold detection processes, output processes, or UI processes. Each DSP process (I have 3 separate 8 channel DSP filters) run in a separate process concurrently with all other processes.

In this project, I will be using some previously designed pieces in conjunction with the FPGA, namely the 18 bit ADC pmod module ( http://www.geotech1.com/forums/showt...Resolution-ADC ) and the Impulse Inspired Flexible TX/RX platform ( http://www.geotech1.com/forums/showt...RX-FE-platform ). At least for the initial effort, the TX/RX is configured for PI-IB mode using a 10 inch co-planer concentric coil.

FPGA based PI Metal Detector:
control signals (TX1 and TX2 for bipolar TX )
control signals for 18 bit 1 Msps ADC
9 samples 8 data channels + EF sample
24 bit 8 channel CIC integration filter: 50 db attenuation stop band
24 bit 8 channel CIC mineralization/ground filter: adjustable in 10 steps 0.0005 Hz – 0.1 Hz
24 bit 8 channel compensation FIR: 60/50 Hz
automatic target threshold employing CFAR technology

Unwanted signal cancellation: There are several sources of signals that we wish to have cancelled out of the final processed signal. Purists will categorize each and have their mathematical solutions for cancelling each. But I only have 2 categories… those that are fast/immediate concerns and those that are static/slow changing. I don’t care about the individual characteristics... only the overall effect.

In the fast category is Earth Field and environmental e.g. electrical interference. That is cancelled out by using a ninth sample taken 5 usec before TX and subtracting that from each of the 8 channel samples.

In the static/slow category is the TX coil decay, ground signal whether normal or highly mineralized ground. These effects are cancelled out by using a long 8 channel filter that is adjustable from 0.1 Hz down to 0.0005 Hz. The output of this filter is subtracted from the corresponding output of the input 8 channel integration filter. During pin-point operation, updates to this ground/mineralization filter is suspended. End result… cancel out everything in each channel that occurs below X Hz and leave any change that occurs above that frequency.

The primary signal process 8 channel filter is adjustable from 60 Hz down to 1.5 Hz.

As the project progresses discussions, results, discoveries will be posted.

[ivconic]

Bravo KingJL!
Moving to a heavier artillery!
Pity that those FPGA modules are not easy obtainable in every corner of this world, it will be tough to follow you.
And the price is a bit above the usual hobby stuff.
But generally i like the idea much!
Eventually a man would want to put all those things together on one pcb... some day.
How much it will drain the power at the end?
...
Personally i would like more if you picked the psoc to continue with the idea.

[KingJL]

Pity that those FPGA modules are not easy obtainable in every corner of this world, it will be tough to follow you.

Yes, it is a pity that availability is limited or restricted in many areas of this world!

And the price is a bit above the usual hobby stuff.

It may well be proved that the LX9 has enough resources to do the job... won't know that until I have it all synthesised. That would cut the cost by almost half. If the LX9 will suffice, hackaday.com has a LX9 shield board for arduino. I think that you could probably put timing and DSP on LX9 and use arduino for UI, signal comparison, threshold detection, output.

How much it will drain the power at the end?

That remains to be determined.. depends on many factors, clocking speed (probably 100 MHz), total area of FPGA used, etc. But in today's world, you are not relegated to carrying around lead acid batteries!

[Mechanic]

I am in the process of implementing an FPGA based PI metal detector. I am using the Xilinx Spartan 6 LX25 FPGA as the basis for this project.
http://www.xess.com/shop/product/xula2-lx25/
http://www.xess.com/shop/product/stickit-mb/
I chose the FPGA route vs the micro-processor (uPC) route due to the demanding DSP requirements and timing requirements. In the uPC route, everything happens sequentially. Even if using interrupt driven processes, everything is sequential and all processes have to share the same overall time limitation (usually the PRT of the TX). In FPGA implementation, each process has it’s own resources and executes concurrently with all other processes. Example: The TX pulse generation and sample request process does one thing; generate accurate timing of TX and sample requests… nothing else. It does not have to share time or resources with any of the DSP processes, threshold detection processes, output processes, or UI processes. Each DSP process (I have 3 separate 8 channel DSP filters) run in a separate process concurrently with all other processes.

In this project, I will be using some previously designed pieces in conjunction with the FPGA, namely the 18 bit ADC pmod module ( http://www.geotech1.com/forums/showt...Resolution-ADC ) and the Impulse Inspired Flexible TX/RX platform ( http://www.geotech1.com/forums/showt...RX-FE-platform ). At least for the initial effort, the TX/RX is configured for PI-IB mode using a 10 inch co-planer concentric coil.

FPGA based PI Metal Detector:
control signals (TX1 and TX2 for bipolar TX )
control signals for 18 bit 1 Msps ADC
9 samples 8 data channels + EF sample
24 bit 8 channel CIC integration filter: 50 db attenuation stop band
24 bit 8 channel CIC mineralization/ground filter: adjustable in 10 steps 0.0005 Hz – 0.1 Hz
24 bit 8 channel compensation FIR: 60/50 Hz
automatic target threshold employing CFAR technology

Unwanted signal cancellation: There are several sources of signals that we wish to have cancelled out of the final processed signal. Purists will categorize each and have their mathematical solutions for cancelling each. But I only have 2 categories… those that are fast/immediate concerns and those that are static/slow changing. I don’t care about the individual characteristics... only the overall effect.

In the fast category is Earth Field and environmental e.g. electrical interference. That is cancelled out by using a ninth sample taken 5 usec before TX and subtracting that from each of the 8 channel samples.

In the static/slow category is the TX coil decay, ground signal whether normal or highly mineralized ground. These effects are cancelled out by using a long 8 channel filter that is adjustable from 0.1 Hz down to 0.0005 Hz. The output of this filter is subtracted from the corresponding output of the input 8 channel integration filter. During pin-point operation, updates to this ground/mineralization filter is suspended. End result… cancel out everything in each channel that occurs below X Hz and leave any change that occurs above that frequency.

The primary signal process 8 channel filter is adjustable from 60 Hz down to 1.5 Hz.

As the project progresses discussions, results, discoveries will be posted.

Hi KingJL,

Now my ears are pricked up! Especially the timing side of things.
Would it be possible for the control side of things to adjust sample timings without effecting the operation of the tx/rx timing?(on the fly)
And in the case where you have many different receive channels, are these easy to adjust/change samples independently of each other? Nested loops in a micro are a real pain.
What timing resolution do you think you will be able to achieve?

Will be interesting to see how you go with this. Good luck! But with good engineering you don't need luck

Cheers Mick

[ivconic]

"...hackaday.com has a LX9 shield board for arduino..."

I saw it in the list, last night when i "googled"-it.

[Ferric Toes]

Hi KingJL,
What you propose sounds really good and I will follow this project with interest. One initial question; will it overcome the dropout in response when a target has a decay that is close to that of the 1/t viscosity ground signal?
One other 'fast category' are magnetised rocks which I have come across in Australia. One rock I have here (0.5lb) has a very strong viscous signal but also has remanent magnetisation such that a paperclip will stick to it. Sweeping a coil over it, causes a blip that rises and falls at the same rate as a true target signal, except that there is no conductive decay and the later earth's field sample catches and subtracts it OK. It's all in the timing and I'm sure your's will do this, but I thought I would mention it as DSP is not my forte.

Eric.

[KingJL]

Would it be possible for the control side of things to adjust sample timings without effecting the operation of the tx/rx timing?(on the fly)

Yes, the timing module will use changeable parameters for each of timing events. I envision a separate concurrent process that handles inputs from the UI and changes parameters accordingly as they happen.

And in the case where you have many different receive channels, are these easy to adjust/change samples independently of each other? Nested loops in a micro are a real pain.

Yes. Basically, the timing module is a state machine... each state has it's own set of parameters for the next event, and the next event causes the machine to advance to the next state.

What timing resolution do you think you will be able to achieve?

The resolution is determined by your clock frequency... My intention is to use 100 MHz clock... The state machine executes the process every clock cycle (you can control if you are processing off of the rising or falling edge)... any and all changes take effect synchronously at the clock edge of the next clock. With an FPGA programming (either VHDL or Verilog) you are describing and implementing hardware logic elements interconnected to achieve your description for each process. Each process has it's own set of hardware resources and it's own timing constraints depending on it's sensitivity list. There is no fetching instructions, execution of instruction, storage of result, etc., etc.

[KingJL]

...
What you propose sounds really good and I will follow this project with interest. One initial question; will it overcome the dropout in response when a target has a decay that is close to that of the 1/t viscosity ground signal?

Eric, I believe so, but that remains to be proved.

One other 'fast category' are magnetised rocks which I have come across in Australia. One rock I have here (0.5lb) has a very strong viscous signal but also has remanent magnetisation such that a paperclip will stick to it. Sweeping a coil over it, causes a blip that rises and falls at the same rate as a true target signal, except that there is no conductive decay and the later earth's field sample catches and subtracts it OK. It's all in the timing and I'm sure your's will do this, but I thought I would mention it as DSP is not my forte.

The timing will be parameter driven and the parameters will be stored on a microSD. The initial design is targeting the following timing scheme: PRF 4000 Hz (25 usec PRT), bipolar TX: PW 50 usec, clamped coil discharge duration ~ 38 usec (coil current = 0 @ ~TX start + 87 usec, EF sample ~158 usec after coil current = 0 (TX start -5 usec). I will be testing with both monocoil and balance IB coils. Initially, I will be focusing on balanced IB to see what info I can glean from samples in the coil decay phase to help in determining valid targets. Initial observations suggest that there is a very "rich" signal during this time. Initially I will be allocating 4 samples during this time and 4 samples during traditional PI RX time (after coil current reaches 0 or thereabout). I am curious about the behavior of the "Australian magnetised rock" with a bipolar TX... maybe your Vallon could answer that.
As far as DSP, there is no real "magic" except that your can define some really sharp filters. Example : the filter process of the initial design has a pass-band of 50 Hz, 0 db, 1 db ripple, and a stop band at 60 Hz, -50 db. In DSP, these values are related to the sample frequency and can be altered on the fly by changing the sample frequency (usually by decimation). So with the above described filter, I can achieve a passband of 60, 30, 15, 7,5, 3.75, 1.875, 0.9375 simply decimating the samples. Also with DSP (depending on how the filter is implemented), you can suspend the filter operation simply by suspending the input samples... every thing justs stops where it is currently. The other advantage of digital processing is the data aquisition... with the ADC we can sample the instantaneous signal at any finite time(within the bounds of the ADC specs). The ADC that is used in the current design samples at the time of CONVST signal, conversion is complete and ready to be shifted out within ~550 nsec, and then powers down until the next CONVST signal. In other words if the CONVST sigbnal occurs at 5 usec, the intantaneouis voltage at that time is seen. Integration is accomplised in the filter, but you are integrating the signal seen at 5 usec. In the analog integrator you are integrating toward the signal level at the end of your sample period (e.g. sample at 5 usec, sample of 10 usec, your are integrating toward the value seen at 15 usec).

[sled]

@KingJL: Cool project!

I also read your thread about the High Resolution ADC and wanted to point out that there are many 24-bit CODECs with the possibility to disable the high pass filter, e.g WM8731 is such an example - used in the X-Terra metal detector (Datasheet: http://www.cs.columbia.edu/~sedwards...udio-CODEC.pdf) see Page 49, "ADCHPD - ADC High Pass Filter Enable". It also supports "raw" parallel output for DSPs, however the sampling frequency of 96kHz might be too low for a PI, but there are codecs going up to 192kHz. Benefit of the audio codec is the cheap price, ~4$ and also multiple channels, plus DAC in one chip.

For FPGA development boards, I had good experiences with the Mojo (https://www.sparkfun.com/products/11953 uses a Spartan 6 XC6SLX9 FPGA, there are cheaper clones for ~40$ on AliExpress).

[KingJL]

@KingJL: Cool project!

I also read your thread about the High Resolution ADC and wanted to point out that there are many 24-bit CODECs with the possibility to disable the high pass filter, e.g WM8731 is such an example - used in the X-Terra metal detector (Datasheet: http://www.cs.columbia.edu/~sedwards...udio-CODEC.pdf) see Page 49, "ADCHPD - ADC High Pass Filter Enable". It also supports "raw" parallel output for DSPs, however the sampling frequency of 96kHz might be too low for a PI, but there are codecs going up to 192kHz. Benefit of the audio codec is the cheap price, ~4$ and also multiple channels, plus DAC in one chip.

For FPGA development boards, I had good experiences with the Mojo (https://www.sparkfun.com/products/11953 uses a Spartan 6 XC6SLX9 FPGA, there are cheaper clones for ~40$ on AliExpress).

I explored the codec approach before I settled on the ADS8881 for the obvious reasons that you stated. I required a minimum of 192Ksps for this application. 192-216Ksps was far less than ideal but acceptable ( and old project manager used to tell all the engineers "Don't let the good get in the way of the acceptable!!" ). I don't think I found one that would allow disabling of the HPF. Another thing, almost all had LPF set at about 50 KHz before I could access the signal. I believe that would preclude it's use in a PI as the BW required for the decay in targets of interest range from about 100 KHz - 1.5 MHz.

The other thing about the codecs as well as most 24 bit ADC's was the power requirements. This was not a "show stopper", but a serious consideration. I wish I could find a 24 bit ADC designed along the lines of the ADS8881. In power down mode (the state it enters at the end of a conversion), it draws only 50 nanoamperes. In the conversion state @ 1 Msps it draws only 2.4 ma (in this application it is in the conversion state for 9 out of 250 usec, a duty cycle of ~3.6%). If a commercial/professionally designed board cannot be found, designing a board layout for a 24 bit ADC/Codec becomes problematic. These 24 bit data access chips are HIGHLY susceptible to noise and at 192 Ksps and above trace length comes into play (especially with differential inputs). A minimum of a 4 layer board layout would be required for a "quiet" 24 bit board.

I continually on the lookout for acceptable higher resolution devices.

[Davor]

It looks to me you'll need a big heat sink on that solution.

[KingJL]

It looks to me you'll need a big heat sink on that solution.

It is really not a "solution". The first objective is to explore, identify, and define what data can be extracted, next how to use that data, then next to optimize and reduce resource requirements, and finally obtain a suitable power source for the final definition. Then it may become a solution!!

[Chet]

I explored the codec approach before I settled on the ADS8881 for the obvious reasons that you stated. I required a minimum of 192Ksps for this application. 192-216Ksps was far less than ideal but acceptable ( and old project manager used to tell all the engineers "Don't let the good get in the way of the acceptable!!" ). I don't think I found one that would allow disabling of the HPF. Another thing, almost all had LPF set at about 50 KHz before I could access the signal. I believe that would preclude it's use in a PI as the BW required for the decay in targets of interest range from about 100 KHz - 1.5 MHz.

The other thing about the codecs as well as most 24 bit ADC's was the power requirements. This was not a "show stopper", but a serious consideration. I wish I could find a 24 bit ADC designed along the lines of the ADS8881. In power down mode (the state it enters at the end of a conversion), it draws only 50 nanoamperes. In the conversion state @ 1 Msps it draws only 2.4 ma (in this application it is in the conversion state for 9 out of 250 usec, a duty cycle of ~3.6%). If a commercial/professionally designed board cannot be found, designing a board layout for a 24 bit ADC/Codec becomes problematic. These 24 bit data access chips are HIGHLY susceptible to noise and at 192 Ksps and above trace length comes into play (especially with differential inputs). A minimum of a 4 layer board layout would be required for a "quiet" 24 bit board.

I continually on the lookout for acceptable higher resolution devices.

Hi KingJL


I have thinking about trying a 24 bit ADC. What is your opinion of the LTC2380-24 mentioned here;


http://www.geotech1.com/forums/showt...542#post211542


Have a good day,
Chet

[KingJL]

Hi KingJL


I have thinking about trying a 24 bit ADC. What is your opinion of the LTC2380-24 mentioned here;


http://www.geotech1.com/forums/showt...542#post211542


Have a good day,
Chet

The specs look good... great in fact. It has a lot features in common with the ADS8881 as far as power consumption and operation. For use in an application like that of the current thread would require that the averaging filter be set to N=1; The only problem I would foresee would be a board layout to minimize noise and ensure stability... I think it would require a 4 layer board to properly implement a successful board design. I think it would be worthwhile to pursue a board based on this IC.

[Chet]

The specs look good... great in fact. It has a lot features in common with the ADS8881 as far as power consumption and operation. For use in an application like that of the current thread would require that the averaging filter be set to N=1; The only problem I would foresee would be a board layout to minimize noise and ensure stability... I think it would require a 4 layer board to properly implement a successful board design. I think it would be worthwhile to pursue a board based on this IC.

Hi KingJL


Thank you for the prompt reply. I will give it a try. One of my concerns is surface soldering such a tiny component. Which I have zero experience with; I will have to try to practice on some cheap parts first.


Have a good day,
Chet