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Originally posted by Chet
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Do you have a hot air station... if you don't, I would not advise that you attempt it... that msop is just too small. A hot air 2 in 1 station can be had for around $60 - $65. With a hot air station and solder paste it is a piece of cake. I did my first smd board (Hammerhead) with only a soldering iron and standard solder... it was successful but it took a long time and was extremely tedious. And that was with SOIC and SOT packages. MSOP is about half the size if SOIC! -
Hi KingJLOriginally posted by KingJL View Post
I have this; YIHUA 8786D Soldering Solder Station SMD Rework Iron & Hot Air Gun; will it work?
http://www.ebay.com/itm/YIHUA-8786D-...Lgfyp4oA4JNLIg
Have a good day,
ChetComment
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Originally posted by Chet View Post
It will work... get some solder paste and some high power magnifiers!!!Comment
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I have the same hot air rework station, you can solder most SMD chips with the soldering iron using a chizel tip. The technique is called drag soldering (http://youtu.be/PUFCDh9BxQU, http://youtu.be/wUyetZ5RtPs). Get some SMD boards out of the junk bin, desolder the ICs with the hot air gun and solder them back as practice. Use lots of flux, that's the key.Originally posted by Chet View Post
Also there are practice boards for SMD between 1$ and 3$ with all kinds of components, free shipping of course.
See here: http://www.aliexpress.com/wholesale?...t=smd+practiceComment
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Hi KingJL, sled
Thank you both for the advice and information.
Have a good day,
ChetComment
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Well, my FPGA board and StickIt MB arrived via UPS today. Meanwhile, I have been coding up the VHDL to implement the Metal Detector. I have coded the main timing functions for the TX pulses (TX1 and TX2) and RX sample requests. The current VHDL is shown in PIMD_Main_vhdl.pdf. I have tried to add enough comments the VHDL to add clarity for others to follow.
The code synthesizes and the run of the code on the simulator testbench results are shown in
I have not yet started the code for the UI, RX filtering, GND/minerilization filtering, threshold detection, CFAR, or detector output. Next I have to generate the FPGA programming bitstream for the current functionality to load into the FPGA. That will let me test out the TX and RX sample requests on the real hardware ( http://www.geotech1.com/forums/showt...RX-FE-platform ).
The plan is to build a UI that responds with LEDs and tones to allow the user to select the parameters to be changed with a mode switch, change the parameters with "+" and "-" switches, go back to normal operation with an End/PinPoint switch. The parameters that can be changed are PRT/PRF (within bounds), filter cutoff (2.5, 5, 7.5, 10,15, 20, 30, 40Hz), RX sample timing (within bounds), threshold, and audio volume to name a few. The UI will be last to implement.Comment
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One determination I have made is that the Spartan 6 LX9 would be more than sufficient for this project. The LX25 is super overkill! I have developed the VHDL for over 50% of the functionality and have used 1,669 out of 30,064 FLIP FLOPS (5 %), 5 out of 52 RAM Blocks (9%), 9 out of 38 DSP48 slices (23%) of the LX25. For the LX9 that would translate to 15% for FLIP FLOPS, 16% for RAM Blocks, and 56% for DSP48 slices. Of greatest concern, when I started this project was DSP 48 multiplier slices which are used extensively by the DSP filters. I have implemented all 3 filters to be used by this application and each filter used 3 DSP48 slices. I cannot see the remaining functionality to be developed requiring 7 DSP 48/multiplier slices.
To date, the following functionality has been developed:
1. The cclock generator process which generates the 100 MHz system clock from the 12 MHz board clock
2. MD timing process, which generates the MD TX pulses and sample requests to the ADC.
3. The ADC driver process which takes the sample requests, starts the ADC conversion, and shifts in the 18 bit converted ADC data for each of the 8 data samples and the EF sample.
4. ADC Service process, which takes the ADC samples (8 data samples plus 1 EF sample. It pre-stages these samples then adjusts ou the EF sample from the data samples before sending the data samples to the Input CIC filter and the GB CIC filter.
5. An 9 channel Input CIC filter which integrates the samples, filters them with an intermediate stop band of 3 Hz - 50 Hz with decimation down to 15 Hz -250 Hz depending on UI selection, for the final FIR filter.
6. An 8 channel GB CIC filter which filters the GB/mineralization path to 0.1 Hz to 0.005 Hz, depending on the UI selection.
7. The GB CIC Filter service process, which takes the output of the GB CIC filter for each sample of the 8 sample channels and stores them in ram.
8. The Input CIC Filter service, process which takes the output from the 8 data sample channels, adjusts out the corresponding GB CIC Filter output, and send the result to the Final FIR filter.
9. The 8 channel Final FIR filter, which filters the adjusted 15 Hz – 250 Hz decimated output of Input CIC Filter and filters to a final bandpass of 2.5 Hz – 40 Hz depending on the decimation rate of the Input CIC Filter that was selected by the UI.
Each of the above processes run concurrently at the system clock speed of 100 MHz.
Left to develop are the back-end processes to compare the collected data, determine threshold detection and Constant False Alarm Rate (CFAR), and determine appropriate output response. Also the processes that constitute the UI that will control the parameters of the MD timing and digital filters.Comment
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Very very interesting project. I've recently purchased some FPGA boards (nexys 4 DDR and Red Pitaya) but haven't had time to do more than the basics on them. FPGAs are great and perfect for metal detecting hardware.Comment
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Hi KingJL
Been try to lower noise level. How are you coming with your project? Wondering if it's easier to lower noise level sampling with an ADC vs an integrator. Adding a GEB sample increases noise quite a bit with an integrator.
greenComment
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Funny you should post now as I was just finishing up a Flow Diagram (which I will probably post when I finish a reply to yours) for the design (as it has now been somewhat sortaed out in my mind). As I have been plodding along with my design. It depend on what you mean by "lowering noise level".not injecting With ADC sampling you are not introducing any (significant) noise providing that you condition the input with an anti-aliasing filter. Using an ADC and then integrating with DSP, you can achieve much better integration. The integration filters that I am using have stop bands that are -70 db. I then follow them with a 2.5 - 40 Hz (user adjustable) FIR filter that has another -40 db of suppression outside of the passband. ADC sampling also has other advantages. In the analog integrator, for small signals, you are integrating up to (but never achieving) the level that is seen ant the END (not the start) of your sampling gate. Hence if you are sampling at 10 usec and your sample gate is 10 usec, then the level you are integrating to is the signal at 20 usec. With the ADC, the sampling capacitor is always following the input voltage and is always charged to the input level. the sampling capacitor is only disconnected during the conversion request. When the conversion is complete, the ADC capacitor is reconnected in following mode. Any noise generated by the connecting/disconnecting the sampling capacitor happens after the value has been captured. The value at the time of the conversion request is the value you will be integrating to with DSP. You can also achieve much higher dynamic range with an ADC than you can with analog providing you use an ADC with enough resolution to minimize the gain you need to provide with the pre-amp. With a 24 bit ADC all you would need is unity gain with an anti-aliasing filter. With my design with a 18 bit ADC, I am using a front end gain of 32. Everything that I have stated are my opinions and understandings that I have developed over 55 years of working in the electronics, and later digital, fields and not to be confused with statements of fact.Originally posted by green View PostComment
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A slight change in course!
Well, after some time out for visiting relatives, a project building 6 doors for the house (still ongoing), and responding to family medical issues, I have gotten back to the design. I have a good portion (timing, integrator, profiler) of the design defined with VHDL code. The control and UI sections were proving complicated to implement with a hardware description. These sections have a a fair amount of calculations (especially division, which takes a massive amount of hardware logic to implement) to perform based on user interactions. These can be defined in VHDL, but the code gets very convoluted and kludgey. For VHDL code to be synthesisable, a signal (hardware register or logic unit) can be driven (written to) by only one process, which means that another process/function cannot modify it. This type of functionality is much better served by using a microprocessor. I had actually thought about eventually making this a hybrid design with hardware doing the timing, integration, profiling while letting the uPC do the control, parameter calculations, and UI.
So, I need a uPC... why not design one into the FPGA (after all, that is basically what a uPC is)? Well , one has been sitting under my nose ( http://www.xess.com/blog/ive-never-b...-1000-of-them/ ) ever since I obtained the XuLa2 FPGA board. It is Arduino code compatible and uses Arduino code libraries and will fit in the Spartan 6 LX25 FPGA along with my hardware logic.
So now, I need to modify my completed blocks to add the uPC communications bus (in this instance, it uses the wishbone bus architecture) so that the uPC can interact with them as hardware peripherals. I get to simplify (and in some cases delete) the control processes that calculated and controlled the timing parameters, filter decimation rates, detector state (initialization, calibration, etc.), and UI by implementing them with software. I have one area that I have yet to formulate a solution; that being how to save the user settings (PRF, filter selection, compensation rate) between powered sequences (using the detector).
I will be posting updates and full source (both VHDL and uPC code) as the design progresses. Basically what I am doing is designing a section, testing it in a live FPGA to make sure the behavior is correct before moving to the next stage. So I will post the development environment zip at these success points.
Here is a functional flow diagram of the FPGA detector with a built-in soft processor.
logic-flow-diagram.pdfComment
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I like your last sentence. I could say the same thing, especially the part about opinion and not to confused with fact. I'm trying to increase S/N by lowering noise level. Sampling seems to be adding noise, I think because of aliasing. An anti aliasing filter needs to have a cutoff frequency less than 1/2 the sampling frequency and be positioned before the ADC. I think sampling with an ADC vs an integrator might be better for the target sample, not sure about the GEB sample. If the preamp doesn't saturate I wonder why gain of 1000 with 13bit ADC is any different than gain of 32 with 18bit ADC. Interested in your project.Originally posted by KingJL View PostComment
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That is true (except for the amplified noise introduced by amplifier circuit). But the real advantage is the dynamic range by using a low gain and high resolution adc. With a gain of 64 it allows me to back up the first sample to 0.5v into the decay curve at the pre-amp output (10mv at the coil). With a 1000 gain you are heavily into saturation at that input. In fact in my design, during the calibration stage, the first sample time is automatically adjusted to achieve that output (0.5v with no target), (actually it is really accomplished by adjusting the TX off time so that I don't have to recalculate all the other samples in relation to the first sample). At a gain of 64 he pre-amp is never in saturation with a coil voltage of <= 90 mv, much more than any target signal. The coil decay profile is subtracted (after the integration filter) from the measured signal leaving only the target signal (if there is any).Originally posted by green View PostComment
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System Overview
To give a little perspective of the Metal Detector Design:
FPGA-based-PI-Metal-Detector.pdfComment
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I went down the FPGA road 3 years ago ... It will either inspire or intimidate you LOL.Originally posted by KingJL View Post
200 Mhz FPGA with 24 bit ADC sampling @ 2.5 Mhz or 16 bit @ 40 Mhz.
50 Mhz MIPS type 32 bit CPU
4 channel VGA Waveform display.
Serial console
Rotary switch encoder.
Pulse generators
Sound synthesiser
LCD driver.
etc etc.
... in the end I went back to $5 Pic32 chip ... it does a better job.
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