Pim Puls .XR 7

[KingJL]

Perhaps it did not matter as the first sample delay was relatively long in these detectors.

Eric.

Eric, do you have the timings for TX, PRT, and A, B, C, D (as referenced on the superdec schematic)?

[eclipse]

Here's the latest version on the schematic - it has the same part ids as the original scanned by Eric.
Only 100K is size, prints & views excellent

Superdec.pdf

[KingJL]

Here's the latest version on the schematic - it has the same part ids as the original scanned by Eric.
Only 100K is size, prints & views excellent

[ATTACH]42138[/ATTACH]

VT also connected to IC1.3 pin 8. Don't know if other omissions or mistakes.

[eclipse]

VT also connected to IC1.3 pin 8. Don't know if other omissions or mistakes.

Good spot! Superdec 1.01.pdf

[KingJL]

Eric, do you have the timings for TX, PRT, and A, B, C, D (as referenced on the superdec schematic)?

I have sorted it out... wasn't sure until verified with sim. as the PRT is relatively long.

PRT:8.8 - 10.8 msec (92.5 - 113.5 Hz PRF)
TX:180 - 860 usec
A (target sample):40 - 140 usec after TX_off (width 56 usec)
B (noise sample):150 - 710 usec after noise sample (width 56 usec)
C (sample):at A and B time, width 56 usec

[KingJL]

I have sorted it out... wasn't sure until verified with sim. as the PRT is relatively long.

PRT:8.8 - 10.8 msec (92.5 - 113.5 Hz PRF)
TX:180 - 860 usec
A (target sample):40 - 140 usec after TX_off (width 56 usec)
B (noise sample):150 - 710 usec after noise sample (width 56 usec)
C (sample):at A and B time, width 56 usec

Forgot D!!
D:0.75 * PRT (width ~105 usec) e.g. PRT=10 msec, D=7.5 msec

[KingJL]

Simulation of the TX/RX

It would be interesting to hear comments about what the seemingly complicated stages in the receive path do, and what the advantages (if any) are there over more conventional analogue circuitry.
Eric.

Here is a simulation of the superdec TX/RX. PRT=10 msec, TX=500usec, A (target sample) 40 usec after TX end, B (noise sample) 410 usec afetr target sample, D 7.5 msec after TX start.




For simplicity, used a MOSFET for TX. X1 of the sim schematic is a module that is made of simulator voltage components to minimize the simulation time. The transistors Q6, Q7, Q8 (TR9, TR4, TR11 of Eric's superdec schematic) form a triggering circuit for the sample timing circuit (IC11b, IC12a. IC12b). This is quite novel as it ensures the start of target sample delay is after the preamp is out of saturation regardless of target strength. In other words the actual sample delay will shift (increase) as target strength increases. I believe that the CA3096 transistor array circuitry provides for a low noise preamp (although the noise of R5 far outwieghs any low noise benefit) and provides a level shifting of the input to virtual ground (VT provided by IC3), allowing much simpler (and probably quieter) power supply design. You will note that the output at TP8 is positive, whereas we are used to a negative output from the front end. Actually, I like the design and think the front end could benefit some of our more modern appoaches.

[KingJL]

Updated simulation

The previous simulation did not correctly model the functionality of IC4, IC5, and IC6 of the superdec schematic. With the previous simulation model, changing the gain of IC4 resulted in the output operating point of IC4 (measured at TP4) to change unacceptably due to the offset currents of IC2 and IC4. I located some models for thee 741 and CD4007 (functional equivalent to MC14007). Now the simulation provides the correct functionality of IC4, IC5, and IC6 by cancelling out the effects of offset currents in IC2 and IC4. As the gain of IC4 is varied from min to max (x1.7, x22 providing total front end gains of x207 and x2680 respectively), the dc operating point (measured at TP4) now stays within 1 mV of -VT and actually varies < 100 uV.

[KingJL]

The transistors Q6, Q7, Q8 (TR9, TR4, TR11 of Eric's superdec schematic) form a triggering circuit for the sample timing circuit (IC11b, IC12a. IC12b). This is quite novel as it ensures the start of target sample delay is after the preamp is out of saturation regardless of target strength. In other words the actual sample delay will shift (increase) as target strength increases.

The start of the target sample delay is held off until the coil input is below 125 mV. Furthermore, the transistors TR9, TR4, TR11 (primarily TR9 and TR4) form a logarithmic feedback path that reduces the preamp gain (IC1 and IC2) of large signals at the coil. Gain reduction (from the original gain of 122) starts when the output of the preamp is more than -1 volt of VT, and is reduced to a gain of 1 at a coil voltage of 2.6 volts. Gain is further reduced by the conduction of TR11 until the preamp goes into full saturation at coil voltages above the battery supply voltage (12 volts).

[Altra]

Good work JL! How does the circuit handle the portion of the signal above battery plus, which is also the positive rail for the op-amps?

Thanks

[eclipse]

Altra JL wrote above that CA3096 shifts the voltage level to VT (which is virtual ground) so you don't need op amp voltage above +Vbatt.

To reduce the noise from R5 perhaps we can implement something like suggested here by moodz?

And perhaps lower noise op amp.

http://www.geotech1.com/forums/showt...130#post179130

...the servo loop in the patent can be dispensed with and a fixed bias on the pass mosfet can be used instead as per the following example .... there is a conventional damping resistor used ( because the current sink is not functional ) Instead of using a messy frontend switch to block the flyback voltage we use the flyback voltage itself to do the switching. The 10 volt bias on the gate of pass mosfet M2 ensures it is hard on except during the flyback period ... note that this bias is higher than the TX voltage of 5 volts. D2 and D9 form a snubber which could be 200volts for example depending on the zener value. A high voltage cap in parallel with D2 will help the snubbing function. D3 prevents excessive negative excursions. W1 is the mosfet sampling switch or you could put the amp here .... The main benefits of this circuit are flyback voltage blocking, no need for switching, low impedance path from coil to first amplifier and simplicity and it may be covered by one or more patents.

[Altra]

Yes, I understand the virtual ground. In PI's the back emf and at least a portion of the decay signal will be above battery plus (coil ground). This is why most PI's have DC to DC converter to shift the positive rail above coil ground. This assumes a N-ch or npn switch.

[KingJL]

Altra JL wrote above that CA3096 shifts the voltage level to VT (which is virtual ground) so you don't need op amp voltage above +Vbatt.

To reduce the noise from R5 perhaps we can implement something like suggested here by moodz?

That has already been done by Minelab (i.e. SD2000). To me, the benifits of that approch is questionable as there are significant gate insertion artifacts to deal with from the "MOSFET SWITCH to the first amplifier."

And perhaps lower noise op amp.

This circuit is very sensitive to the op amp used. It tends to get unstable when the current feedback reduces the gain to extremely low levels ( < 10 ). Since this occurs before the start of target sample delay has been signaled, it is of no consequence. However, using better performing op amps seems to increase this tendency to the point that the signal given to IC11b pin 8 unreliable.

Right now, I am not really trying to improve the circuit... just trying to understand and analyze what is going on.

[eclipse]

Yup will be building the original without any modifications too, well maybe try a mosfet instead of the PNP.
Too bad all chinese fabs are closed and I will have to wait one more week to place an order due to Chinese NY.

[KingJL]

Yup will be building the original without any modifications too, well maybe try a mosfet instead of the PNP.
Too bad all chinese fabs are closed and I will have to wait one more week to place an order due to Chinese NY.

[ATTACH]42171[/ATTACH]

Be careful about using the MOSFET. I used it in the simulation for simplicity, but the MOSFET simulation does not model the coss. When the coss of the MOSFET has been added via an external capacitor (120pf for the one I used), the instability of the circuit described above becomes worse because the damping effect of R4 has decreased, again affecting the signal to IC11b pin 4. Typical MOSFETs have even larger coss values, hence even more degradation. Sticking to the transistor eliminates this complication.