Pim Puls .XR 7

[KingJL]

Be careful about using the MOSFET. I used it in the simulation for simplicity, but the MOSFET simulation does not model the coss. When the coss of the MOSFET has been added via an external capacitor (120pf for the one I used), the instability of the circuit described above becomes worse because the damping effect of R4 has decreased, again affecting the signal to IC11b pin 4. Typical MOSFETs have even larger coss values, hence even more degradation. Sticking to the transistor eliminates this complication.

In my simulations using a MOSFET with coss added, I found that you need to increase the coil inductance to maintain stability. For a MOSFET with abut 120 -150 pf, I found a coil of about 1200 uH was needed to perform reasonably without having to change any other circuitry. For a MOSFET with the coss of a IRF740, I would expect 1500 - 1800 uH to be required.

[eclipse]

Good info, thanks. I will try option 1: STP20NM50FD (Coss 290pf + 2K2 damping resistor to reduce oscillations); and option 2 will be the default: 2N3773 (2N4348 cannot be found in reputable stores)

[KingJL]

Good info, thanks. I will try option 1: STP20NM50FD (Coss 290pf + 2K2 damping resistor to reduce oscillations)

That should work... use the sim files I supplied in the last sim run add the coss in parallel with the MOSFET and view the signal at label "IC11b pin 4". If that is as good or better than the original, then you can have confidence in your approach. But remember, simulation does not equal real world performance. But it can give you confidence of what to expect.

[KingJL]

This circuit is very sensitive to the op amp used. It tends to get unstable when the current feedback reduces the gain to extremely low levels ( < 10 ). Since this occurs before the start of target sample delay has been signaled, it is of no consequence. However, using better performing op amps seems to increase this tendency to the point that the signal given to IC11b pin 8 unreliable.

This observation seemingly can be reduced by the selection for D3. I do not have a model for a BY206, but of the models available, an ES1D seems to reduce the amplitude these oscillations about half.

[Orbit]

Oryginal coil Pimdec .Superdec .. is 780uh .

[chafik]

Good info, thanks. I will try option 1: STP20NM50FD (Coss 290pf + 2K2 damping resistor to reduce oscillations); and option 2 will be the default: 2N3773 (2N4348 cannot be found in reputable stores) ill
why not trying a SIC MOSFET like SCT10N120 i didn't see any project using SIC Mosfet because they are pricey and still new

[KingJL]

Oryginal coil Pimdec .Superdec .. is 780uh .

That makes things a LOT more stable and predictable!

[eclipse]

why not trying a SIC MOSFET like SCT10N120 i didn't see any project using SIC Mosfet because they are pricey and still new

SIC mosfets are driven with different gate voltage and it's 1200V. Also this one seems not to be able to handle Avalanche mode well so it's not a good candidate for this application.
I've done real world tests with several higher voltage mosfets (1000V) and in all my tests I couldn't get better results than good old 1$ IRF740.

[eclipse]

One more update on my drawings: SUPERDEC 1.02.pdf

[Ferric Toes]

Amazing work everybody!!!

I have had four days break in Oxford with a family re-union and hoped that investigation of this interesting circuit would continue in my absence. It has exceeded my expectations and it will take a few days more to read and understand the posts. The Research Laboratory for Archaeology in Oxford was where I first helped develop PI, starting in 1966, so there is a special connection to the place. Plus Oxford has some excellent watering holes and my favourite, The Lamb and Flag, is still there.

Eric.

[KingJL]

... The transistors Q6, Q7, Q8 (TR9, TR4, TR11 of Eric's superdec schematic) form a triggering circuit for the sample timing circuit (IC11b, IC12a. IC12b). This is quite novel as it ensures the start of target sample delay is after the preamp is out of saturation regardless of target strength. In other words the actual sample delay will shift (increase) as target strength increases...

I did a sim run to demonstrate the above described behavior. The run modeled a 5 usec tc target. The run uses a step command specifying the target to coil coupling of 0.001, 0.005, 0.01, 0.05, and 0.01 to simulate increasing target strength.



The green traces show the pre-amp output and the red traces show the signal fed to IC11b pin 4. The trailing edge (positive going) of the red trace triggers the start of the target and subsequent delays.

[Orbit]

Finally revived after 27years .

[Ferric Toes]

Some comments were made earlier about the coil damping and the lack of a resistor connected directly across the coil. It is a long time ago to recall, but I am sure there is no actual resistor inside the coil housing. What I am sure of, and which I remember surprised me at the time, is that the coil was wound with enamelled single core wire. The wire gauge was such that cross-sectional eddy currents were themselves having a damping effect and this was observed when I tested a coil on one of our other PI detectors at the time. There was no shielding in the coil.

I wonder if a Vallon VMH3CS coil would work in this circuit? It has 1.5mH inductance, 3.4 ohms and 0.53mm solid enamel wire. Perhaps it would even work with a mosfet.

Eric.

[Ferric Toes]

Finally revived after 27years .[ATTACH]42191[/ATTACH]

Well done! Is it working, such that you can post waveforms? Can you measure your coil resistance and post the value?

Eric

[Orbit]

Well done! Is it working, such that you can post waveforms? Can you measure your coil resistance and post the value?

Eric

Hi Eric ! I do not have an original coil I tried it with a coil Goldscan 4 but I have data in hdd on the old scheme ( 780uh Q 0.60mm ) when I have time I can measure it and post waveforms !
Otherwise works solidly and stable !