PLL driven power oscillator with f-to-V conversion

[Teleno]

The objectives of this circuit are:

(a) to provide an oscillator that works with a 5V power supply but can oscillate at a relative high peak voltage of 40V,

(b) to track tiny changes in frequency by converting them to a voltage signal with high gain.

The high voltage oscillation makes the tank very sensitive to targets (when measured by changes in amplitude). The high voltage is achieved by using low values of C and high values of L. Driving the tank from the ground side allows the use of low voltage transistors.

The heart of the project is the (in)famous CD4046 PLL. If the Phase Comparator 1 is used, when the chip's center frequency (fo) is the same as the tank's resonance frequency the voltage at the VCOin pin (triangle wave) dances around Vcc/2 with a 50% duty cycle. The VCO signal is then in quadrature with the input signal from the oscillator, which when buffered, is what we need to drive the transistors of the half-bridge.

When the VCO and the input signals are locked there's still a fixed phase error that causes switching artifacts at the transistors. An RC network between the VCO and the comparator's input introduces a compensation delay so that the transistors are switched on and off at the exact moment that the current in the coil crosses zero.

The PLL is configured with high R1 and low R2, which provides a narrow frequency locking range, and therefore large excursions of the control voltage VCOin for small changes in the tank frequency, which can form a base for target discrimination.





Now the million $$$ question: How to get rid of the steps at the peak of the signal? (V(osc) in green)




They are caused by the cross-over current peaks at Q5 and Q6 (red and blue traces) not being equal. The difference charges the capacitor C1 of the tank (peaks in the blue trace), causing the sudden voltage steps in the signal.

Any ideas on how to tame them?

You can play with the simulation file attached. It contains a good model of CD4046B, use the inc. command to include it in your sims.
I will also share the equations to work with the CD4046:

fo = (Io + Ic) / (2 x C x (Vcc/2 + 0.813))

where:

Io = (Vcc - 1.14) / R2
Ic = 0.695 / R1

The ratio Io / (Io + Ic) gives the locking range in % of fo.

[waltr]

Yep, typical "cross-over distortion".
Read about how to eliminate this in audio push-pull driver circuits- there is a lot of info.

Simple fix that might work is add diodes in series with R2 & R3 to the VCO out drive. The diode compensate for the transistor's Emiter diode drop is is where the distortion is coming from.
However, it also seems you have the transistor in the wrong places. The npn should be on top and the pnp on the bottom. This puts their emitters together and the diode ensure one of the transistor is always conducting. Again look up audio push-pull amps.

Interesting idea so keep us posted.

[Davor]

I think you won't be able to remove glitches even if you turn the device into a linear regime. But it does not necessary make a problem for the purpose you are pursuing.
I'd go with a Colpitts if high voltage is a goal.
Also I think mikebg's idea of regenerative detector is worth re-examining. So instead of a PLL you'd have an regenerative amplifier, and perhaps a quenching circuit. Such configuration may work well in LF.

[Teleno]

Davor, you're right. This is not typical crossover distortion, it's due to the fact that on end of the tank swings from 0 to Vcc while the other stays always at 0, that's why the step equals Vcc. I've tried the typical approach of biasing Q6 and Q5 to conduct at all times but it doesn't help a bit.

[Skippy]

Have you though about tapping the TX coil in order to achieve the high TX power/voltage? Then the L,C,R values of the tank can be chosen for sensible Q values.

This TX tapping is used by Georgi (Nexus) , there is a thread on here where he showed some circuit diagrams.

For the digital power amplifier, you should look into the 'totem pole' output stage, used in logic buffer circuits.
Would including the power output stage inside the feedback loop of an op-amp circuit help make it behave better, eg. less glitches?

[Teleno]

Also I think mikebg's idea of regenerative detector is worth re-examining. So instead of a PLL you'd have an regenerative amplifier, and perhaps a quenching circuit. Such configuration may work well in LF.

The regenerative detector needs complicated and unstable manual adjustments, it's very iffy. This circuit is more stable and increases the sensitivity of two signals: amplitude and a voltage proportional to the tank's frequency. This is all you need for discrimination.

Have you though about tapping the TX coil in order to achieve the high TX power/voltage? Then the L,C,R values of the tank can be chosen for sensible Q values.

This TX tapping is used by Georgi (Nexus) , there is a thread on here where he showed some circuit diagrams.

I haven't tried it and I can't find that post. In any case the .zip file contains the LTSpice schematic, you can play with it and post your results.

[Davor]

It may surely work, but Colpitts with two capacitors does the same job without the knitting job.

I found the mikebg schematic, and you'll see he liked regulation. I think building the device in a super regenerative fashion (allowing oscillation, but quenching it periodically) could do the trick without any kind of regulation. The point is that the onset of oscillation is highly volatile process, where minute differences can play a big difference in detected signal, and however crude they may seem, SR receivers are very sensitive. Their shortcoming in every other possible use is the oscillator emission, while in MD it may only be an advantage.

See how Tx is in fact your oscillator in disguise:

[Davor]

And BTW, super regenerative receivers have self-AGC nature comparable to log amplifiers - perfect for MD.

[Teleno]

Certainly, the tank is connected just the same, the only difference being the triggering is provided by the phase and amplitude coupling from a target. I suppose there's a certain discrimination from the fact that targets not providing the right amplitude AND phase will not trigger oscillation.

Anyway, it's a completely different project and I prefer the predictability of the PLL plus the possibilities of mathematical treatment (MCU) of the freq. and amplitude components.

The CD4046 alone gives quadrature at the center frequency only. I like a version of the PLL oscillator you posted long ago using a Johnson counter so that true Q and I signals are available at all frequencies of the tank. The transistors can then be switched a the zero crossing at all frequencies.

Since I'm working with, 85-90Khz (my target is gold nuggets), the Johnson counter version would require almost 200KHz from the VCO. The CD4046 can hardly deliver that. I'd have to move to a 74HC4046 which has different - but more predictable) configuration formulas.

[Teleno]

I've found the solution: swap the L and C components, replace A1 by and inverting buffer.

The spike is now 300mV instead of 5V, but the DC component of Vosc is now Vcc/2, not a problem though.

[Tim]

Great stuff Teleno. Looking forward to further developments in this thread.

[Teleno]

The SPICE model for CD4046 I provided has a bug: PC2out (Phase Comp. II out) is pulsing between Vdd/2 and Vss, not between Vdd and Vss as it should.
I looked at the netlist but couldn't figure it out. I think node "e" which is set at Vdd/2 might have some relation to it.
Anyone has a netlist-to-schematic onverter to have a look at what's going on?

[Teleno]

The SPICE model for CD4046 I provided has a bug

I withdraw that, it works fine.

[Davor]

I have a completely different 4046 model, based on a hierarchical model. Funny but it also had some problems, and I fixed them. Let me check where I put it...
Here, this is the last-known-good model that worked properly, and even gave results comparable to reality. Put 4046.asc and 4046.asy into a folder your schematic is, and simply use the symbol. You may as well make your own symbol, but this one work as well. If you ever wish to obscure what's inside it, use a netlist of 4046.asc and rename it to .sub.
This model does not have the "tri-state-amplifier" for analogue input, but I modelled the Vdd related resistance... kinda works OK.

[Davor]

One more thing, to use this model properly, you must define a parameter VCC, which this model uses for digital levels.