what is Self Adjusting Threshold

[Carl-NC]

If there is an input offset then, yes, the integrator will have a slight ripple, but still very close to DC.

[Mr.Jaick]

No, when the switch turns off the voltage across the cap remains, then slowly discharges through the feedback R. If you remove the feedback R, the voltage would just stay there, as a DC value. The R is needed for drift stability.

Hello Carl
now there is a question.
imagine there is no feedback R and NO DC Offset from preamp nor the integrator itself to gradually saturate the "Pure Integrator" with no feedback R, wouldn't it be better to use the pure integrator instead of the lossy one ?
for example the non-inverting integrator with no feedback versus the usual inverting lossy integrator.
why almost everyone using the lossy integrator instead of the lower noise non-inverting version ???

[Carl-NC]

I think by "non-inverting integrator" you really mean the sample-hold demodulator (SHA), which is not really an integrator. Here are the two methods:



The sampling integrator is widely used in PI designs and the SHA is widely used in VLF designs. I don't know why this is the case because, in simulations, both methods produce the same results. Many years ago I built a circuit with both and seem to recall that the integrator gave a little better results but I don't recall why.

In any case, the SHA is lossless during hold but does not perform a true integration during sampling. And the integrator does truly integrate but is not lossless during hold. I think neither of these are important issues and you can probably use either method with equal success.

[Mr.Jaick]

Many years ago I built a circuit with both and seem to recall that the integrator gave a little better results but I don't recall why.

perhaps because of better SNR due to integration
thank you for your insight as always, I very appreciate it.
BTW what software do you use to draw these schemes?
is it easy to use?
I'd like to present nice and clear schemes in my future discussions.

[Carl-NC]

I've done noise sims on both circuits and see no difference. But there may be something that does not show up in sims.

I use Microsoft Visio which is a general drawing tool. It is not a "schematic entry" tool but it does make pretty drawings which is what I used for the ITMD book. It's very easy to use.

[green]

I think by "non-inverting integrator" you really mean the sample-hold demodulator (SHA), which is not really an integrator. Here are the two methods:



The sampling integrator is widely used in PI designs and the SHA is widely used in VLF designs. I don't know why this is the case because, in simulations, both methods produce the same results. Many years ago I built a circuit with both and seem to recall that the integrator gave a little better results but I don't recall why.

In any case, the SHA is lossless during hold but does not perform a true integration during sampling. And the integrator does truly integrate but is not lossless during hold. I think neither of these are important issues and you can probably use either method with equal success.

Sample time and sample rate effect gain doesn't affect frequency response with Sampling integrator. Sample time and sample rate effect frequency response doesn't affect gain with Sample-and Hold circuit. Some PI's have Sample rate and sample time adjustments, maybe a reason PI's use the Sampling integrator?

[Qiaozhi]

perhaps because of better SNR due to integration
thank you for your insight as always, I very appreciate it.
BTW what software do you use to draw these schemes?
is it easy to use?
I'd like to present nice and clear schemes in my future discussions.

An alternative to Micosoft Visio is the free and open-source vector graphics editor known as Inkscape.
I used that to create the diagrams in the Arduino Nano PI book.
Inkscape is supported in Linux, Windows, and macOS.

[Melbeta]

Well, lets see now, if I can understand it, based upon Compass Electronics "Automatic self tuning threshold" circuit. First you tune in the threshold sound, then you flip a switch, throwing it into SAT??? The SAT, maintains the pre-set threshold audio????? Now if that is not it, it is something other then what Compass Electronics introduced years ago.
Melbeta

[Carl-NC]

Sample time and sample rate effect gain doesn't affect frequency response with Sampling integrator. Sample time and sample rate effect frequency response doesn't affect gain with Sample-and Hold circuit. Some PI's have Sample rate and sample time adjustments, maybe a reason PI's use the Sampling integrator?

You are correct, and I should say that my sim comparisons were done on a VLF application where timing was always 50%. When you get into short-duration sample pulses the SI method may have an advantage. I built a comparison circuit at White's and took some notes on it (which stayed with White's and were probably thrown away ) and all I recall is that the SI method had better results for some particular case but I don't remember what. I've intended to build another dual circuit but it's not high on my list.

[Carl-NC]

Well, lets see now, if I can understand it, based upon Compass Electronics "Automatic self tuning threshold" circuit. First you tune in the threshold sound, then you flip a switch, throwing it into SAT??? The SAT, maintains the pre-set threshold audio????? Now if that is not it, it is something other then what Compass Electronics introduced years ago.
Melbeta

That's an entirely different animal. We're talking about demod circuits, the threshold/SAT comes afterwards.

[GeoMax]

@ Electronic Design Software

I used many electronic design program like Eagle, Orcad, Protel, Altium, Mentors, Kicad and others in the past. But the program Diptrace convinced me sofar the most. Diptrace is an easy to use software and has all most practical features you really need to draw 1 or 2 page circuits like metal detector circuits has. I use Diptrace for drawing small circut snippets like Carl do with his VISIO software. The adwantage compare to the usage of VISIO is that I can use my prior drawn circuit snippets in a real design with copy/paste right away and do not need to draw it agian and again from scratch. Further, I drew with diptrace about 70++ circuit snippets of partial circuit parts which I usually use in my designs and I can rapidly deploy them in a new design.

Check it out, Diptrace has also a free version which is not limited to board size like Eagle.

[Mr.Jaick]

Sample time and sample rate effect gain doesn't affect frequency response with Sampling integrator. Sample time and sample rate effect frequency response doesn't affect gain with Sample-and Hold circuit. Some PI's have Sample rate and sample time adjustments, maybe a reason PI's use the Sampling integrator?

Voila...
now things start to make sense!
this means you can't have wide sample / narrow sample combination to achieve proper ground balance or target conductivity processing with the SHA method!
so imagine using all sort of sample widths for different signals like ML does on their PIs or Garratt ATX, with the use of SHAs it would not make sense because now the long GEB sample doesn't mean more gain on GEB channel it just means faster response time than let's say the 15 us Gold sample thus no quiet ground balance
however it might work on something like TDI where you have identical sample widths and control the GEB gain after integrators.
thank you Green for your post.

[Mr.Jaick]

have anyone tried using two SAT stages?
I think I have seen something like that but that was in a VLF design
I think using two SAT stages will lower the low frequency noise a bit
but since it will shift the signal I wonder if the detector would sound weird..!
let's say for example : Integrator => SAT => (Filter + Gain) => SAT => (Filter + Gain)

[Carl-NC]

In VLF detectors they are called differentiators and there are usually 2 of them (so-called 2-filter designs). The Goldscan/TDI design has a second SAT stage after the ground balance stage. It's exceptionally slow so you don't really hear it.

[Mr.Jaick]

yes double differentiation in some VLF designs
other than attenuating the lower spectrum of 1/F noise and circuit drift, is there other advantages to using another slow SAT?