Single capacitor integrator switch placement

[Qiaozhi]

I have redrawn the LTSpice schematic to make it more readable, and made the following changes:

1. Set the main input to a steady 110mV.
2. Set the EFE input to -10mV, so that the extracted target signal should then be 100mV.
3. Set the main sample width to 100us, with a 10us delay.
4. Set the EFE sample width to 100us with a 650us delay.
5. Set the TX pulse period to 1ms.

In the first image you can see the opamp output settles to around -500mV, but with a lot of noise in the signal (1C integrator from Eric.png).
The second image shows a zoomed-in version of the plot window, which shows the noise consists of glitches in the waveform (Waveform glitches.png).

As an experiment, I then added two 470nF capacitors at the drain connections of the jfets (With extra capacitors.png). As you can see, the opamp output is much cleaner than before.
The fourth image shows that the output settles at -500mV, which indicates that the circuit has a gain of 5 (Gain of 5.png).

The simulation file is also attached for your delectation.

Comments?

[dbanner]

Delectation.

[Qiaozhi]

Also, you can achieve a glitch-free output by simply adding a lowpass filter at the output of the opamp (22k + 470nF).
Don't forget to remove the two extra 470nF caps.

The output signal should then settle to -500mV, as before.

[green]

I have redrawn the LTSpice schematic to make it more readable, and made the following changes:

1. Set the main input to a steady 110mV.
2. Set the EFE input to -10mV, so that the extracted target signal should then be 100mV.
3. Set the main sample width to 100us, with a 10us delay.
4. Set the EFE sample width to 100us with a 650us delay.
5. Set the TX pulse period to 1ms.

In the first image you can see the opamp output settles to around -500mV, but with a lot of noise in the signal (1C integrator from Eric.png).
The second image shows a zoomed-in version of the plot window, which shows the noise consists of glitches in the waveform (Waveform glitches.png).

As an experiment, I then added two 470nF capacitors at the drain connections of the jfets (With extra capacitors.png). As you can see, the opamp output is much cleaner than before.
The fourth image shows that the output settles at -500mV, which indicates that the circuit has a gain of 5 (Gain of 5.png).

The simulation file is also attached for your delectation.

Comments?

Do you have a formula for the integrator TC?

[Altra]

Clever adding the extra capacitors, made a big improvement. Would these need to be matched in a real circuit? I believe in Eric's actual circuit the integrator is followed by an RC low pass, which should also remove the output noise? Maybe a series 10K with a 100n to vref?

Add: Sorry didn't see post #78 while responding

[Qiaozhi]

Clever adding the extra capacitors, made a big improvement. Would these need to be matched in a real circuit? I believe in Eric's actual circuit the integrator is followed by an RC low pass, which should also remove the output noise? Maybe a series 10K with a 100n to vref?

See post #78, where I added a lowpass filter at the opamp output (22k + 470nF), and removed the two extra caps. See attachment.

[Qiaozhi]

Do you have a formula for the integrator TC?

The integrator time constant should simply be RC. i.e. 22k * 470nF = 10.34ms.

If you're talking about the TC of the exponential output of the integrator, then this is heavily affected by the sample rate.
In the simulation I used sample pulse widths of 100us, and a pulse period of 1ms. By dividing the pulse width into the period we get a value of 10.
In this case, 10 * RC = 103.4ms, which looks correct from the waveform plot.

If you modify the main and EFE sample pulse widths by increasing them to 200us, the TC becomes 5 * RC = 51.7ms, and the waveform reaches -500mV in half the time.

[6666]

delectation

[green]

The integrator time constant should simply be RC. i.e. 22k * 470nF = 10.34ms.

If you're talking about the TC of the exponential output of the integrator, then this is heavily affected by the sample rate.
In the simulation I used sample pulse widths of 100us, and a pulse period of 1ms. By dividing the pulse width into the period we get a value of 10.
In this case, 10 * RC = 103.4ms, which looks correct from the waveform plot.

If you modify the main and EFE sample pulse widths by increasing them to 200us, the TC becomes 5 * RC = 51.7ms, and the waveform reaches -500mV in half the time.

I get about 52ms looking at your simulation with 100us samples not 103.4ms you suggested.

[Ferric Toes]

Many Thanks, George, it makes things a lot clearer now. I didn't appreciated the fact that the resistor networks around each gate are effectively in parallel as both 2K2 resistors go to 0V (no signal) on the cross coupled inverter outputs, and which will reduce the gain to 5. Apologies to Green who was correct on this

The glitching looks terrible on the simulation, so I had a look with my analog 'scope. . I presume the parasitic capacitance of the jfets are responsible. Anyway it is quickly damped and negligible compared to the sample width. As these glitches are synchronous with the pulses I expect that their effect is negligible. I will try a filter on the output to see what minimum is necessary to get rid of the ringing.

Eric.

[Qiaozhi]

I get about 52ms looking at your simulation with 100us samples not 103.4ms you suggested.

Now I look at it again more closely, I think you are correct. Theoretically the tau should be 51.7us, as the calculation needs to be divided by 2, in the same way as the resistor-based gain calculation.

Have a look at the attached image and simulation. I've added a behavioral voltage source with the equation:



A few things to note:

1. The parameter "t" is replaced by "time".
2. There is an offset that matches the final value of Vout. (i.e. -500mV)
3. The initial starting value (V0) has to be higher than the plot for Vout, otherwise the two waveforms don't align properly.

[dbanner]

Capacitative loading can be on the input side or output side or both. Can this ringing be caused by the capacitative loading of the scope probe coax itself?
Very interesting topic guys.

[dbanner]

Second question, does it matter where the compensation is applied in relation to the source of the capacitative loading? Should issues involving input side capacitance loading be remedied on that side or doesn't matter.

[green]

Many Thanks, George, it makes things a lot clearer now. I didn't appreciated the fact that the resistor networks around each gate are effectively in parallel as both 2K2 resistors go to 0V (no signal) on the cross coupled inverter outputs, and which will reduce the gain to 5. Apologies to Green who was correct on this

The glitching looks terrible on the simulation, so I had a look with my analog 'scope. [ATTACH]50649[/ATTACH]. I presume the parasitic capacitance of the jfets are responsible. Anyway it is quickly damped and negligible compared to the sample width. As these glitches are synchronous with the pulses I expect that their effect is negligible. I will try a filter on the output to see what minimum is necessary to get rid of the ringing.

Eric.

R8*C2=22us works good with Qiaozhi's simulation

[green]

I know nothing about metal detecting, just trying to learn something metal detectors. One benefit of this integrator is being able to change the filter response if coil size is changed. Example: response is adjusted for a 30cm coil, switch to a 15cm coil. Thinking response needs to be faster. Sample time needs to increase to make the response faster. Thinking increasing sample time is opposite of what I should do, maybe wrong?