Direct Sampling Front End for MD's (PI and VLF)

[KingJL]

The idea to use an audio ADC as a direct sampling front end for metal detectors began about 9+ years ago when I obtained a sample Cirrus Logic CS5381. The CS5381 had a 120dB dynamic range and signal/noise ratio, which seemed extremely attractive as far as a front end for a metal detector. The exceptional dynamic range is result of the high bit count of the ADC (24 bits for the CS5381). The exceptional signal/noise ratio is a result of a very high oversampling rate (6.144 MHz) filtered and decimated down to the output sample rate (192 KHz for the CS5181). The issues at that time were difficulty interfacing with the affordable micro processors available, the need for external single ended to differential buffers for the input signals, and the timing constraints/granularity (~5.2 usec/192KHz f/s for the CS5381). At that time you almost needed an FPGA as a middleman to interface the audio ADC to the micro.

Fast forward to today… there are inexpensive processors today that have processing peripheral modules that make the interface with the audio ADC more feasible and some even have Configurable Logic Cell (CLC) peripherals to further enhance the interface and processing capabilities. My two goto processors are the 8 bit PIC18F47Q84 and the 32 bit PIC32MK0512MCJ064. Both have the availability of CLC’s. Also today there are audio ADC’s that are easier to interface with, have more features flexibility, and a much broader timing range (~1.3 usec/768kHZ fs for the TLV320ADC5120).

This project is centered around the TLV320ADC5120 (available fro LCSC for $2.39 ea.). The TLV320 has integrated input buffers that are software configurable for single ended or differential input and have a software configurable gain of 0 – 42 dB. The ADC output data size is configurable as 8, 16, 24, or 32 bit. Output sample rate f/s is software configurable up to 768 KHz ( multiples and sub-multiples of 48 KHZ). Software configuration communications interface is via I2C. Data is transferred via SPI.

To facilitate proof of concept, software development, and testing of various PI and VLF MD configurations (now expanding to include half sine hybrid PI/VLF), I have designed a TLV320ADC5120 Test/Evaluation board. I provide it free to the community in hopes that you may find it useful to try/test out new ideas for direct sampling of PI and VLF MD’s. Both of the processors previously mentioned will easily interface with it. Both processors have relatively inexpensive evaluation boards available (the PIC18F57Q84 (also the PIC18F57Q43) Curiosity nano and the PIC32MK-MCJ Curiosity-Pro).





Schematic, Gerbers, BOM attached

[Dean Sarelius]

Hi King,
I would like to purchase one of your evaluation boards. Let me know the price and delivery and how I should send you the payment.
Cheers

[Dean Sarelius]

Hi King,
After taking a closer look at the specs on the TLV320ADC5120 it appears that it can only accept up to 3.6V input range which is too small for my application so might pass for now.
Thanks for the offer anyhow..cheers

[KingJL]

Hi King,
I would like to purchase one of your evaluation boards. Let me know the price and delivery and how I should send you the payment.
Cheers

Dean Sarelius (and everyone else) I was not offering any PCB's for the TLV320ADC5120... I had posted the gerbers, schematic, and BOM for anyone that may be interested. JLCPCB will manufacture 5 boards for $2.00 - $3.93 plus shipping.

[KingJL]

Hi King,
After taking a closer look at the specs on the TLV320ADC5120 it appears that it can only accept up to 3.6V input range which is too small for my application so might pass for now.
Thanks for the offer anyhow..cheers

I don't know what your application might be, but for direct sampling 3.6V input range should be more than enough to accommodate the usable signal from the RX coil. That being said, the focus of the "TLV320ADC5120 TEST/EVAL" is for evaluation and proof-of-concept of the use of high performance audio ADC in MD's. I would also imagine any actual inclusion of the audio ADC in an MD design would use a re-designed layout with much shorter signal paths for the MCLK & SPI / cpu connections, as these are a relatively high signaling rate.