Phase margin(op amps)

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For op amp stability, common design practice is to have a phase margin,



Anyone done actual calculations on some MD circuit examples, to figure out the phase margin of some of these closed loop circuits? Since it does affect the step response (overshoot and ringing) we need optimal design but also the derivations in math, with data from published datasheet, so a true comparison can be made and performance evaluated.

In order to refine or improve the circuit. We know that capacitance loading of the output should be avoided or at least kept as low as possible. Also on the inverting input, since the pcb trace can also introduce instability due to some small capacitance. We sometimes notice some guard traces around the input pins.

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Some theory:
The Phase Margin is the difference between the phase lag , for an amplifier output signal(relative to its input) at zero dB gain ie. unity gain, or that the output signal has the same amplitude as the input.



Measure of stability

- How close the system is to a phase shift in

- Phase of when gain of = 0 dB

-A zero or negative phase margin at a frequency where the loop gain exceeds unity (1) guaranties instability.

Also, there would be a lot of ringing with a step function input when the Phase Margin is low. So it is a very important consideration.

Most op amps are internally compensated which ensures dominant pole frequency response, but there are some which require external compensation. It would seem that the roll off rate will affect the phase margin calculations at 0 dB. I haven't gone into the math as yet. I will struggle I think.

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20dB per decade, these bode plots, dam. The dominant frequency pole.

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[Carl-NC]

I have not paid much attention to phase margin but probably should, especially with uber-fast PI circuits. It is probably only an issue in the preamp as everything post-demod is basically DC with super-low bandwidths. Even VLF preamps are probably not critical as they are usually run with a fast opamp (for noise reasons) but with a low dominant pole set by the feedback tau. So you are unlikely to hit the opamp pole before crossing 0dB. Fast PI preamps, however, use very fast opamps and very little feedback comp cap (sometimes none at all), so the dominant pole is set either by the opamp or by parasitics.

Every time I've seen guard rings, it's on retune circuits where leakage current is critical.

[Daves]

I have not paid much attention to phase margin but probably should, especially with uber-fast PI circuits. It is probably only an issue in the preamp as everything post-demod is basically DC with super-low bandwidths. Even VLF preamps are probably not critical as they are usually run with a fast opamp (for noise reasons) but with a low dominant pole set by the feedback tau. So you are unlikely to hit the opamp pole before crossing 0dB. Fast PI preamps, however, use very fast opamps and very little feedback comp cap (sometimes none at all), so the dominant pole is set either by the opamp or by parasitics.

Every time I've seen guard rings, it's on retune circuits where leakage current is critical.

Carl,
1)What are the criteria for the opamp used in the rx input?
2)What are the criteria for the opamp used in the analog demodulator stages?
3)If we are doing direct sampling and the 1st opamp in the rx input is used for buffer, the 2nd opamp is used for differential & fixed gain, what are the criteria for the opamp?

There must be a reason why the same opamps are used in some detector models.

[Carl-NC]

1a) VLF & PI: sufficient gain-bandwidth, low noise, supply voltage
1b) PI: slew rate, overvoltage recovery

2) Depending on the demod design, mostly low input bias current, usually a JFET or CMOS opamp. i prefer rail-to-rail output, 1-3MHz BW.

3) You usually want the 1st stage to have some gain to relax the noise requirement of stage 2. Otherwise, same as 1a.