VLF MD with digital signal processing : Bee-Buzz 1

[Atul Asthana]

Because without a clear "scenario" this kind of work cannot even be successfully started... let alone finished!With a small difference that I have already decided on ESP32 and not bluepill.
But take this with a grain of salt, it's always on a very long stick with me...long shot as the Americans say.
I started to come up with a scenario. These days I'm very slow to put together a concept. It will be a very long process. Due to certain private difficulties I am prevented from working faster. zz0.5jpso9el75azz

Ivconic,
your explanation and documents are excellent knowledge.

I have a suggestion.
the generic definition and explanation that I am trying to develop for this vlf md, can apply to all kinfs of Hardware.
You could develop your product based on some variation of the explanation I am putting together.

Regards
Atul

[ivconic]

Your "scenario" in your post #58 is a pretty good start.
But Carl is also right; you have to clarify all the details better.
I am also working on my "scenario".
But I'm much slower and I'm always "looking for a hair in the egg"! (local slang saying)
I am too persistent in the details that my wife is sick of me for a long time!
I do not write my "scenario" integrally in one text.
I'm rather breaking down the details of the project on many more levels.
People around me are mostly sick of my hair splitting...
When I said I preferred ESP32 over STM32... know that was "yesterday"!
Today (now it's 4:40 early in the morning, I woke up with the computer again) and today I think completely differently than yesterday.
Instead of just writing my current decision... you'd better look at this document I put together (not for the forum but for my own personal use):

[Atul Asthana]

Your "scenario" in your post #58 is a pretty good start.
But Carl is also right; you have to clarify all the details better.
I am also working on my "scenario".
But I'm much slower and I'm always "looking for a hair in the egg"! (local slang saying)
I am too persistent in the details that my wife is sick of me for a long time!
I do not write my "scenario" integrally in one text.
I'm rather breaking down the details of the project on many more levels.
People around me are mostly sick of my hair splitting...
When I said I preferred ESP32 over STM32... know that was "yesterday"!
Today (now it's 4:40 early in the morning, I woke up with the computer again) and today I think completely differently than yesterday.
Instead of just writing my current decision... you'd better look at this document I put together (not for the forum but for my own personal use):

thinking, rethinking and wiping out and rethinking are a part of life, thats how innovations happen.

[Atul Asthana]

I don't understand #6. Can you provide a timing diagram that shows the relationships? Also, what will the PWM signal look like, and how will you create it?

the pwm output will be genersted by loading corresponding sineeave value into the pwm register on each 384 khz interrupt (the second ticker). the pwm register will then use count down/compare internal function to generate required pulsewidth.

when passed through a lowpass or bandpass filter, in our case a 6 khz bandpass/tuned circuit, it will look like a sinewave, with some distortion (less than 60dB).

[Carl-NC]

One thing you should try to avoid is manually controlling timers. STM timers can be set up to create autonomous arbitrary waveforms via DMA. See STM App Note AN4776. Once you have it set up, the timer runs completely autonomously with no further need to intervene in code. It therefore has zero impact on code execution. If you set up your timing properly, you can also use one of the other channels to autonomously trigger the ADC.

[Atul Asthana]

One thing you should try to avoid is manually controlling timers. STM timers can be set up to create autonomous arbitrary waveforms via DMA. See STM App Note AN4776. Once you have it set up, the timer runs completely autonomously with no further need to intervene in code. It therefore has zero impact on code execution. If you set up your timing properly, you can also use one of the other channels to autonomously trigger the ADC.

I am not too familiar with the modes of the timers (in fact, I am unfamiliar with the whole of stm32 processor specialities. my other engagements are much more and are much more taxing, and are not even remotely connected to anything here), but by bruteforce, I can possibly get it working to a satisfactory level, with advantage of some portability to other microcontroller arhitectures like esp32 etc, though I am not aiming for it.

to simplify the scheduler, I will run the internal ticker at 96 khz, that is :
generate 16 point pwm sine wave and sample the rx wave 16 times.

though this will increase the thd of tx wave ie 18 khz (-10 to-15 dbc) and 30 khz (-20 to -25 dbc), but I have three filters : tx tuned circuit, rx tuned circuit and a single pole band pass in the rx amplifier to filter out this noise. Considering the filtering effect of the tuned coils+opamp filter (5 poles in total) in this design, the 3rd and 5th harmonics will likely be suppressed by -40 dBc or more, possibly even below -60 dBc. This is significant and helps reduce scheduler design complexities.

in fact, if I improve the Q of both tanks, I can probably get still better dupression of the harmonics.

And, sampling the rx signal at 16 points, instead of original 8 gives added advantage of noise reduction (equivalent of 1 bit resolution). My calculation is that theoretically, I should be able to derive 3+4 bits of additional gain, provided the noise is incoherent with the signal. But in our case, we may get 4 - 5 bits at the best. And I think thats pretty good and sufficient for the project in its present form.

this scheme will reduce my need to further learn something about something that I am not too familiar with.

for the rx front end design, I've asked one of my analog design friends to help out. I may also need to approach some one with some experience on stm32 programming to further reduce my load. let us see if I can find some one who can implement your suggestion of running the pwm+adc independently.

[Atul Asthana]

I'd request more experts to advise so that, we can start at a good enough level of designed performsnce, and can try achieving real performance as close as possible to theoretical designed performance at the lowest possible cost and lowest possible complexity.

[Atul Asthana]

VLF Metal Detector DSP V0.1
(31 Dec 2024)

Aim and Objectives:

The project aims to create a "somewhat" commercial-grade VLF metal detector using the STM32F103C8T6, prioritizing hardware and software simplicity while achieving reasonable depth and discrimination.

Design Aspects:

TX Coil Design:
Diameter: 10 inches.
Wire: 22 AWG.
Turns: 25.
Estimated Inductance: ~223 µH.
Target Resonant Frequency: 6 kHz.
Tuning Capacitor: ~315 nF (to achieve resonance at 6 kHz).
DC Resistance: 0.84 Ω
Impedance at 6 kHz: 8.44 Ω
Q Factor: 10

RX Coil Design:
Diameter: 10 inches.
Wire: 28 AWG.
Turns: 40.
Estimated Inductance: ~678 µH.
Target Resonant Frequency: 6 kHz.
Tuning Capacitor: ~104 nF (to achieve resonance at 6 kHz).
DC Resistance: 4.8 Ω
Impedance at 6 kHz: 26 Ω
Q Factor: 5.3

TX Signal Generation: A 6 kHz sine wave is approximated using 16-point PWM, driving an H-bridge powered by 5V. PWM duty cycle modulation controls transmit power (50-250mW range).

RX Front-End Amplifiers:
Two-stage non-inverting amplifier using the OPA2376.
Stage 1: High input impedance buffer and moderate gain (around 30). AC coupled to the RX coil using a 1uF capacitor.
Stage 2: Additional gain (around 37) and bandpass filtering.
Sallen-Key Bandpass Filter: Center frequency 6 kHz, bandwidth 15% (900 Hz), Q ≈ 6.67. This filter is implemented around the second op-amp of the OPA2376.
Output AC coupled to ADC with a 1uF capacitor and biased to 1.65V using a voltage divider.

Data Acquisition/Sampling Methodology:
The STM32's internal ADC is used.
Sampling Frequency: 16 samples per 6 kHz cycle (96 kHz).
16 consecutive cycles are sampled.
Corresponding points from the 16 cycles are summed. This provides a 12dB SNR improvement from averaging, and 9dB from oversampling.

Signal Processing:
Fixed-point Goertzel algorithm (optimized for single-cycle processing) extracts amplitude and phase.
Two 16-tap Butterworth IIR low-pass filters are applied to the amplitude and phase outputs of the Goertzel algorithm. One filter extracts the slowly changing "ambient" ground response, and the other extracts the faster changing "target" response.
VDI is calculated based on the phase difference between the ambient and target responses.

Noise Mitigation
Low-noise op-amps (OPA2376).
Tuned TX and RX coils for pre-filtering harmonics.
Sallen-Key bandpass filter.
Oversampling and averaging.
Synchronous detection (using Goertzel phase output).

Total Signal Dynamic Range and System's Dynamic Range:
Estimated Signal Dynamic Range: The target signal is estimated to be between 1 µV and 4 mV (72 dB) at the receiver coil input.
System's Dynamic Range: The system's dynamic range will be primarily limited by the noise floor of the receiver. With careful design and the noise mitigation techniques described, a noise floor of around 1 µV or slightly less might be achievable. This would give the system a dynamic range close to the signal's dynamic range (around 70dB or slightly more). The averaging and oversampling will improve the dynamic range by 21dB.

Contentious Issues/Trade-offs:

16-point PWM still introduces harmonics, though significantly attenuated by the tuned coils and filter. Increasing PWM points would reduce harmonics but increase processing.
The bandwidth of the Sallen-Key filter is a trade-off between selectivity and signal strength. A narrower bandwidth improves selectivity but reduces the signal amplitude.
The computational cost of the 16-tap IIR filters is a consideration on the STM32F103C8T6. Optimizations will be necessary.
Without DMA, the ADC sampling and processing must be carefully timed to avoid missing samples.

Hardware Connections:

TX Coil H-Bridge:
PA0: PWM output (Timer 2 Channel 1) - H-bridge input 1
PA1: PWM output (Timer 2 Channel 2) - H-bridge input 2
H-bridge power: 5V

RX Coil Amplifier Input:
PA2: Analog input (ADC Channel 2) - Output of the RX amplifier
Buttons (9 total):
PB0 - PB8: Connected to the buttons. Configure these pins as inputs with internal pull-up resistors enabled.
Speaker:
PA8: PWM output (Timer 1 Channel 1) - Connected to the speaker through a transistor or small audio amplifier.

Power LED:
PC13: Output - Connected to the power LED through a current-limiting resistor (e.g., 220 Ω).
Error LED:
PB9: Output - Connected to the error LED through a current-limiting resistor (e.g., 220 Ω).

This description provides a complete overview of the metal detector's design, including the specific hardware and signal processing choices as of 31 Dec 2024.

[Repwoc]

Signal Processing:
Fixed-point Goertzel algorithm (optimized for single-cycle processing) extracts amplitude and phase.

What is the advantage of using the Goertzel algorithm over sampling the RX waveform at the zero-crossing and wave peak points to determine phase and amplitude? I can see that the Goertzel algorithm is good for detecting if specific frequencies are present in a signal, but you already know what frequency will be there and you just need to know the phase shift and amplitude change. It seems like a large processing overhead for no obvious benefit.

paul

[JoyJo]

Greetings! Gentlemen, Merry Christmas and Happy New Year to all! If we talk about the topic of signal digitization: what is the difference in using a special ADC chip or an audio codec? How is the audio codec better or worse than the classic ADC?

[Carl-NC]

Mostly the CODEC is just a cheap way to get a decent 24b ADC. CODEC ADCs are usually sigma-delta and typically have an SNR of 100dB or so for as little as $3. A 24b SAR has about the same SNR for $15-50.

[Atul Asthana]

What is the advantage of using the Goertzel algorithm over sampling the RX waveform at the zero-crossing and wave peak points to determine phase and amplitude? I can see that the Goertzel algorithm is good for detecting if specific frequencies are present in a signal, but you already know what frequency will be there and you just need to know the phase shift and amplitude change. It seems like a large processing overhead for no obvious benefit.

paul

thanks for bringing up this point.

zero crossing + peak detection is very susceptible to noise,

• Frequency Specificity: Goertzel precisely isolates the 6 kHz frequency component, rejecting noise and interference at other frequencies, while zero-crossing + peak detection is more susceptible to broadband noise.
• Noise Resilience: Goertzel's inherent filtering properties make it more robust to noise than simple peak detection, which can be easily triggered by noise spikes.

In a metal detector, the noise figure is critical as it determines whether a target can be detected or missed. To address this, I plan to incorporate a 24-bit audio codec, as recommended by Carl, to improve the noise performance.

Additionally, oversampling the waveform provides a significant advantage in noise reduction compared to using only two samples for a 6 kHz signal. By sampling the waveform at 16 points, the noise can be reduced by 9 dB, allowing detection of targets with signals up to 8 times weaker. This improvement, achieved through oversampling and the Goertzel algorithm combined, outperforms the traditional zero-crossing and peak-detection methods.

kindly opine. we need lots of nitpicking, advise and suggestions to improve this md, while keeping the costs, complexities and component counts low.

[moodz]

There are quite a few starting points on the web ... that will save time. A modular approach will be most beneficial. ( TX FRONTEND, RX FRONTEND, ADC BLOCK, DSP BLOCK, USER INTERFACE BLOCK, POWER BLOCK )
and you need system and signal flow diagrams rather than word essays.

eg. This was done in 3 weeks ? and well documented.

GitHub - teiturhelgi/VLF-Metal-Detector: Very Low Frequency Metal Detector designed and built as a project for three week course in Electromagnetics at DTU.


just sayin ... moodz.

[Atul Asthana]

What is the advantage of using the Goertzel algorithm over sampling the RX waveform at the zero-crossing and wave peak points to determine phase and amplitude? I can see that the Goertzel algorithm is good for detecting if specific frequencies are present in a signal, but you already know what frequency will be there and you just need to know the phase shift and amplitude change. It seems like a large processing overhead for no obvious benefit.

paul

I am aware of the following methods of amplitude and phase extraction, of which, I've used all except wavelet transform. fft was a very common spectrum analysis methodology for machinery vibration analysis, Goertzel was used in fsk/psk demodulation, zerocrossing for power control using triacs, PLL for frequency syntheciser, quadrature sampling for am nbfm demodulation. I dont recall how I used hilbert, but was probably for machine vibration analysis.

here are the methods, their computational load, susceptibility to noise and best use scenario :

Method, Computational Load, Noise Susceptibility, Best Use Case

Fourier Transform, Moderate to High, Moderate, Wideband analysis

Goertzel Algorithm, Low, Moderate, Single-frequency detection

Zero-Crossing/Peak, Very Low, High, Low-complexity scenarios with high SNR

Hilbert Transform, Moderate, Moderate, Precise phase and amplitude tracking

Phase-Locked Loop, Low to Moderate, Low, Real-time phase tracking in noisy signals

Quadrature Sampling, Low to Moderate, Moderate, Direct amplitude and phase calculation

Wavelet Transform, High, Low to Moderate, Non-stationary signals or detailed analysis

Zero crossing reuires high snr signal, and our problem is to identify and extract target in very low snr scenario.

[Atul Asthana]

There are quite a few starting points on the web ... that will save time. A modular approach will be most beneficial. ( TX FRONTEND, RX FRONTEND, ADC BLOCK, DSP BLOCK, USER INTERFACE BLOCK, POWER BLOCK )
and you need system and signal flow diagrams rather than word essays.

eg. This was done in 3 weeks ? and well documented.

GitHub - teiturhelgi/VLF-Metal-Detector: Very Low Frequency Metal Detector designed and built as a project for three week course in Electromagnetics at DTU.


just sayin ... moodz.

yes, good amount of work done and information collected in the project document.

Have you made it? hows the performance?

This is still an exploratory project where we are researching various aspects, with everything under review and nothing finalized yet. Once the hardware, methodology, and other details are clear, we’ll formalize it into a project document.

My target audience includes metal detector users and experts who have in-depth knowledge of the technology. Unlike a student project aimed at beginners, this project requires a different approach—focusing on core aspects like noise figures and dynamic range rather than covering the basics. The goal is to discuss essential elements and leverage expert insights of users/designers to refine the design.

With this in mind, I am specifically looking for explicit references to noise figures, dynamic range and distortions in the quoted student project. What noise figures have these students quoted in their project?

btw, I read that esp32's adc is not very linear and this reduces senstivity, injects harmonic noise. "
The ADC of the ESP32 has a – fully justified – bad reputation.

• The advertised 12 bits are practically 9 bit +3 bit noise.
• The V/ADC relation is not linear
• The first 0.21V of the input (by 11dB attenuation) are ignored"

1. https://github.com/e-tinkers/esp32-a...ster/README.md
2. https://stackoverflow.com/questions/...ading-on-esp32
3. https://esp32.com/viewtopic.php?t=2881
4. https://forum.arduino.cc/t/fixing-th...n-esp32/699190