Hi bbsailor,
your proposals needs to be investigated deeply. And I see therein much potential to increase the signal-noise-ratio (SNR) and the stability of detecting.
I have allready planned a computer simulation about the amplifier and demodulator stage of the PI and the implementation of the lock-in amp.
Do you know the timings from gate 52 to 57 (on page 1)?
window 1:
gate for non-inverting signal: 52
gate for inverting signal: 53
window 2:
gate for non-inverting signal: 54
gate for inverting signal: 55
window 3:
gate for non-inverting signal: 56
gate for inverting signal: 57
Unless I don't know the timing behaviour, I can not say, if there is more potential to get. This is necessary for me to analyse, how the "lock-in" in the demodulator stage is implemented and whether there is room for further enhancements.
Aziz
your proposals needs to be investigated deeply. And I see therein much potential to increase the signal-noise-ratio (SNR) and the stability of detecting.
I have allready planned a computer simulation about the amplifier and demodulator stage of the PI and the implementation of the lock-in amp.
Do you know the timings from gate 52 to 57 (on page 1)?
window 1:
gate for non-inverting signal: 52
gate for inverting signal: 53
window 2:
gate for non-inverting signal: 54
gate for inverting signal: 55
window 3:
gate for non-inverting signal: 56
gate for inverting signal: 57
Unless I don't know the timing behaviour, I can not say, if there is more potential to get. This is necessary for me to analyse, how the "lock-in" in the demodulator stage is implemented and whether there is room for further enhancements.
Aziz
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