NEW !!! Full differential PI front end.

[moodz]

Thanks for the update, Moodz,

I would like to add to your last sentence:COILS

The best signal processing will not be able to make a good detector out of a bad coil. A GOOD COIL IS NEEDED.
Anybody is capable of building a more or less coil. but to build a good coil, considerable experience is needed.
To build a really good coil cost efficiently, proper installations and testing facilities are needed.

I therefore propose:

We build a few coils of different parameters as open source projects, here on the forum.
Once the FPGA signal processing block is fully developed and for sale, some of the excellent coil manufacturers may be interested in producing the specific coils for the TMPI.

In fact, I would be much interested to know who the coil manufacturers are.

Which coils are recommended by forum members?

Which coils are the best?

Is it worth paying for the best coil? How much difference is there in coil performance with the same machine?

Tinkerer

Good point Tinkerer ... dont forget FRONT ENDS ... the FPGA will only do the digital bit past the ADC.

Moodz.

[IBGold]

Hi Tinkerer,
The best coils are the ones that every detail is done with precision I can take up to four days to make one coil but every one uses the best materials that I can source for the job and great care is taken on the assembly and the way it is done but as my time is my own and the coils are not commercial but for me it does not matter I have the best coils I can get and the fun of making them but I will say that the 3 to 1 rectangular and the Duel Field are my favorites and they blow commercial coils away on performance its all in the construction details, but I am not doing it as a living, I am about to start on a prototype differential mono for Moodz to try when we tidy up a few details.
Regards, Ian.

[moodz]

FPGA update

IBGold is working on a coil to use with the TMPI / FPGA .... thanks Ian. I have started looking more closely at the Tinkerer and/or Aziz descrimination method and one thing becomes very clear ... the current system has a 14 bit ADC however in order to get sufficient sensitivity the gain is set to 100. This is good for sensitivity but is bad for dynamic range. At a gain of 100 the dynamic range is reduced to about 12 millivolts with a sensitivity of a few microvolts however this is not really able to handle the sampling requirements when you want to resolve microvolt levels on a several hundred millivolt waveform.
So the ADC input for the DSP system now moves to 24 BITS
The internal bit length of the DSP code in the FPGA is 32 bit so this fits in with no code changes.
This enables the system to handle an input of 2 volts but still resolve down to uVolt levels. The base sample rate is approx 6 MSPS. Because the resolution of the ADC is now 1000 times higher than the 14 bit ADC ... the gain can now be minimised or dispensed with. The 24 bit ADC has dual differential inputs so no changes are required to work with the differential front end.

Below is a pic of the board ( 1 inch square ) and fitted to the FPGA board.
There arent many pins because the data is clocked out serially by a 40 Mhz clock. There are separate supplies and grounds for the analog inputs on the 24 bit chip ... not connected in the pic yet.

moodz

[Tinkerer]

TMPI COILS

Hi Tinkerer,
The best coils are the ones that every detail is done with precision I can take up to four days to make one coil but every one uses the best materials that I can source for the job and great care is taken on the assembly and the way it is done but as my time is my own and the coils are not commercial but for me it does not matter I have the best coils I can get and the fun of making them but I will say that the 3 to 1 rectangular and the Duel Field are my favorites and they blow commercial coils away on performance its all in the construction details, but I am not doing it as a living, I am about to start on a prototype differential mono for Moodz to try when we tidy up a few details.
Regards, Ian.

Hi Ian,

I fully agree with you. To build a single good coil can absorb days of work. This is why I believe that to sell coils, they need to be build by a commercial outfit, that can invest in research and development, tools, gigs and testing installations.
With all that it is still hard to produce high quality, reliable, long lasting coils at a good price.

Are there any recommendable coil manufacturers in Australia? Anywhere else?

Where could one order say 100 coils, made to stringent tolerances?

Tinkerer

[Tinkerer]

S/N, INCREASING SIGNAL AMPLITUDE

Moodz,

sampling with 24 bit really opens a new horizon.

I have been improving on the S/N a bit. More signal amplitude to start with.

Attached are 3 scope pictures of the RE_PI Coil # 5 output NO AMPLIFICATION.

Settings: Vertical 200mV, Horizontal 5uS

Pictures:
No Target
4"x4" alu foil
4"x5" 1/16th steel plate.

Targets 60mm above the coil.

The coil is sitting on slightly magnetic red fire bricks, 35cm above the concrete floor that contains re-bar mesh. This serves as simulation of iron mineralized ground.

These targets can be considered near maximum range.

Tinkerer

[moodz]

FPGA progress

Good work Tinker ... the 24 bit ADC is up and running ... only took 10 lines of code .. could not believe it ... The 14 bit chip was more like 100.

So I now have two fully differential 24 bit channels at my disposal. The chip was only $8.
The protoboard, caps and pins added another $2 ... so a fairly cheap investment at $10 for 24bit goodness.

The input voltage limit is 2.8 volts +/- ( tho I will limit to +/- 1 volt ) and the real sampling window is 5 uS though the internal rate is several Mhz. So your screen shots are at the optimal levels for input to this ADC.

The pic below shows the 4 channels purple, yellow, white and red running on the VGA display output from the FPGA engine. I have not put a real signal yet as I tried this with the first chip and spiked it .... some flyback from the coil must have leaked ...
I am sure a liberal sprinkle of diodes will fix this.

The display shown is at maximum resolution 64 uV per division. Equivalent to a few hundred uV peak to peak. The Channel 1 an 2 input are open so we are just looking at noise and EMI hitting the ADC inputs. Did not need to touch the DSP code.

I will now have to include the ADC in the front end circuitry ( maybe on a chip carrier so it can be easily replaced if it gets spiked ).

Moodz

[Tinkerer]

24 bit ADC

Hi Moodz,

your progress goes in giant steps.

The input voltage limit is 2.8 volts +/- ( tho I will limit to +/- 1 volt ) and the real sampling window is 5 uS though the internal rate is several Mhz. So your screen shots are at the optimal levels for input to this ADC.

Do you have any specific reasons to limit the input voltage to +/- 1V? It would be much easier for me to have 2.8V +/- headroom.
The CRO shots are raw and not amplified. I would much like to do some filtering and amplification, within the +/- 2.8V.

Tinkerer

[hobbes_lives]

Which ADC?

Hey Moodz,

What's the part number of the 24-bit ADC that you are now using?

[moodz]

24 bit ADC

Hey Moodz,

What's the part number of the 24-bit ADC that you are now using?

Wolfson Microelectronics WM8786

I clock them at a 200x oversample for an effective external sample at 200 Khz = 5 us

They are very easy to interface to FPGA in Master Mode as the chip generates all the timing signals and the data clocks itself in.

moodz.

[moodz]

Hi Moodz,

your progress goes in giant steps.

The input voltage limit is 2.8 volts +/- ( tho I will limit to +/- 1 volt ) and the real sampling window is 5 uS though the internal rate is several Mhz. So your screen shots are at the optimal levels for input to this ADC.

Do you have any specific reasons to limit the input voltage to +/- 1V? It would be much easier for me to have 2.8V +/- headroom.
The CRO shots are raw and not amplified. I would much like to do some filtering and amplification, within the +/- 2.8V.

Tinkerer

The input is rated at 2 volts RMS ... 2.8 volts pp. Filtering is what the DSP does naturally ... amplification should not be needed that is why we are using 24 bits .... uVolt sensitivity with filtering by DSP. so if the signal is 1.000000 volts and it moves to 1.000001 volts ... should be able to detect it.( more complex than this but you get the drift )

Moodz.

[hobbes_lives]

Hi Mootz,

I don't follow what you mean here...

I clock them at a 200x oversample for an effective external sample at 200 Khz = 5 us

I was reviewing the datasheet for the WM8786, and it looks like it can only be configured for a maximum sample rate of 192kHz. In master mode, the oversampling ratio can be set to 128fs or 256fs. If you don't mind, can you please explain in more detail how you have the WM8786 configured?

Thanks.

[moodz]

Hi Mootz,

I don't follow what you mean here...



I was reviewing the datasheet for the WM8786, and it looks like it can only be configured for a maximum sample rate of 192kHz. In master mode, the oversampling ratio can be set to 128fs or 256fs. If you don't mind, can you please explain in more detail how you have the WM8786 configured?

Thanks.

Hi Hobbes .... a long time ago I read an article how you could overclock microprocessors by tuning up the voltages and the input clock ( we are talking Z80s here so more than 20 years ago ) I have overclocked every computer I have ever had since then ....

To cut a long story short I dont particularly pay too much attention to data sheets ... you can clock the chip at whatever will work.. This chips specs the maximum master clock at 40 Mhz however to adhere to digital audio standards you must use the specific clocks ... but hey ... I am not doing audio here so I use whatever does it for me. This particular chip will clock all the way up to nearly 50 megs but starts to miss a few conversions ... this is equivalent to approx 380 Ksps

I was clocking at a higher frequency because I had not bothered to code the FPGA clock for the required clock ... so I just used the nearest.

However I am now using the correct clock ... as I realised there is no need for overclocking.
The input clock is set now to 24.576 Mhz for oversample of 128fs where fs is the desired sample rate of 192 Khz.
So 128 x 192000 = 24576000 ... ie 24.576 Mhz

However 192 Khz is plenty fast for this application this equates to a time BETWEEN samples of 5.208 us .... The sample and hold window is much faster than this ... so we only need to slide the phase of the ADC clock to sample at precise points on the RX waveform. The sample window is well under 1 us ... it is the conversion time that takes up the rest of the time till the next window.

This means we can use these cheap chips in place of much more expensive and faster ADCs because we are controlling the point at which a sample is initiated by controlling the phase of the clocks ...

Moodz.

[moodz]

FPGA update

the FPGA project has split across two boards now ...
The new board is much smaller .. sucks less power ... but will still have the same horsepower in the DSP department ..

The larger green board is the current development system. The smaller red board is the new development system split. This board is $US 50 which is a 1/3 of the cost of the larger board. It will still have the VGA waveform output capability.

Shortly I will post a block diagram of the system as I know some of you are having trouble following what we are talking about.

moodz

[simonbaker]

I need to retire so I can get my head around this stuff. It's good.

What do you think the min power required ultimately would be for a detector based on these boards?

Regards,

-SB

[moodz]

The min power is very hard to peg ... for instance the big board draws about 220 ma at 5v which is just over 1 watt. The smaller board draws half that. However you have to consider that the power consumed by an FPGA is related to the complexity and how fast the clocks are. Similiar to a CPU the more you work it the more power it consumes. You can however design to turn off clocks in unused parts etc. Because this design is a PI I would expect energising the coil to consume the bulk of the power.
There are next generation FPGAs around that will draw much less than these chips used here.

moodz.