NEW !!! Full differential PI front end.

[moodz]

I guess that if I can get the FPGA project completed ... we will be able to compare some real world results.

moodz

This paper sums up the waveform analysis process used in the DSP code .... no requirement for FFT.
See page 4. ( excellent explanation )

mags.pdf

[moodz]

FPGA update.

Someone went and bought up all the AVNET spartan 3a boards. Cant buy them online any more.

I will have to revert to Spartan 3e 500 starter board by Digilent for now. No problem .... it will still work.

The pulse generator code has been upgraded to run off a 200 Mhz clock ... this provides 5 ns resolution on pulse timing. I was originally running a 1 us resolution however when you get up close and personal with the flyback pulse the 5 ns gives you alot more dance space ( actually 200x more ). It can also be modulated on a pulse to pulse basis .... this may turn out to be important down the track.

The front end drive circuitry has been designed, simulated and awaits installation with other bits in a field box. The front end will use bipolar pulses ... I thought for a moment I would be in trouble with a Bruce Candy patent US6653838 where he seems to be citing bipolar pulses as one of his claims .... however the good old Corbyn patent has bipolar pulses so I am back in business again. ... Corbyn specifies a "dual field" TX coil also ... I will chase that one up with Carl ...hmmm.

moodz

[Aziz]

and the following things are ( because I accidently pressed submit too early ... he he )

1. One or more pulse generators that can be numerically controlled ( duty cycle and frequency ). Obviously need this to control the MOSFET switching. However my initial design will be very similiar to an older minelab.

2. One or more ADC drivers to get analogue data into the system.

3. One or more DAC drivers to generate analogue signals either for feed back to amplifier front end, coil balancing, meters .... whatever.

3. One or more rotary knob controller so you have user controls.

4. A sound synthesiser for user alerts and maybe music during lunch breaks.

5. one or more LCD driver so you can display stuff . ( 2 x 16 char currently )

6. Multichannel VGA digital oscilloscope so you can see signals not only what the ADC captures but also results of DSP computations. Also very useful for checking coil performance etc. This single feature alone is the most useful to have as you can see if your design works or not ... in the field.

7. VGA also displays text console so you dump lots of info about things that wont fit on LCD.

8. serial port so you can connect to computer. On the larger Xilinx Board there is ethernet and more RAM / Flash also.

9. A 32 bit MIPS compatible RISC processor on the FPGA for user code. ( the fast DSP is done in FPGA though ... more efficient) This does the menus, reads the rotary knob values, controls the displays and maybe does the high level descrimination.

10. DSP code blocks that can switched into the signal chain ...

11. All of the above is coded inside the FPGA, tested and works and I have only used up 59% of the resources of a cheap ( $20 ) FPGA.

moodz.

Hi moodz,

have a look into this patent:
http://www.google.com/patents/about?...BAJ&dq=6927577

Aziz

[moodz]

Hi moodz,

have a look into this patent:
http://www.google.com/patents/about?...BAJ&dq=6927577

Aziz

ouch ouch ouch ouch and ouch ..... this is almost exactly the design of the FPGA PI processor . I had to read this 4 times ....however they made one crucial mistake ... the english language is wonderful how the meaning of things can be totally different by the use ( misuse ) of a single word. The primary claim ( and dependant claims ) uses the word "mode" to imply that the detector has different states ( ie fine calibration mode, course calibration mode and detect mode ) My detector is always in detect mode so I am safe ... according to my personal patent attorney ..
The FPGA determines the calibration data by removing the target data from the signal. Not the other way round .

close shave ... but thanks for alerting me to this Aziz !!!

Regards,

Moodz.

[Tinkerer]

Is this patent not basically doing the same thing?

http://www.geotech1.com/forums/showp...04&postcount=3

Tinkerer

[moodz]

Is this patent not basically doing the same thing?

http://www.geotech1.com/forums/showp...04&postcount=3

Tinkerer

That one is expired ??? ..... amazing how all these patents re-patent parts of earlier patents. How long do US patents last anyway ...

[Tinkerer]

That one is expired ??? ..... amazing how all these patents re-patent parts of earlier patents. How long do US patents last anyway ...

This whole patent scheme is really collapsing. With the Internet it is possible to find so much more "prior art" that it is really difficult to invent something new. However, this does not seem to prevent some companies of misusing the patenting system to eliminate competition.

Most of these patents would not stand up to litigation, but deep pockets to pay good lawyers seems more important than honesty in patent applications.

I was of the opinion that discussing ideas on the open forum would classify an idea as "prior art". However, not even older patents seem to be respected as "prior art".

So, should we worry about infringing patents? We don't want to expose ourselves to bullying tactics by the "patent grabbers".

Lets look at a new idea, a new and innovative way to skin the cat.

We do not sell a metal detector. We sell an Electromagnetic Pulse Testing Platform. EPTP

The platform consists of an FPGA brain and many peripherals, designed to test and analyse mineral ground response, ground conductivity and homogeneity as well as ground contamination by metals etc.

The platform can transmit a great variety of electromagnetic pulse sequences and shapes through a great variety of transducers and sensors, coils, probes and arrays.

DSP software samples and analyses the response captured by the transducers, sensors, coils, probes and arrays and produces a variety of outputs, audio, digitally stored, visual, oscilloscope etc.

The EPTP is sold in modular form. The FPGA brain with a basic firmware and
a basic transducer/sensor.
The EPTP can then be upgraded and expanded with additional firmware and more peripherals.

There is virtually no limit to expansion modules that could include GPS, Laptop, temperature sampling, soils acidity/alkalinity, etc., etc.. even cold beer dispenser. Ooops, change the last one to cold milk dispenser, we don't want to mess with alcohol laws.

Anyway, I hope they don't patent this idea. Maybe we should discuss the pros and cons a bit so it becomes public knowledge and "prior art".

Tinkerer

[moodz]

FPGA update

Changed the pulse generator back to 100 Mhz clock ... step size is 10 ns .. 0 to 65535 ( 16 bit control ) or 0 to 655.35 us in .01 us steps.

The sample clock is 1.3 Mhz and the pulse repetition is 196 us or 5.098 Khz .... pretty high for a PI but lots of samples = lots of sensitivity.

Now the question is how many sample points ????

1 sample during transmit.
1 early sample just after fly back
1 mid sample 50 to 100 us
1 late sample at 196 us

How to process ???

moodz

[Aziz]

What about a DSP?

Could make things easy.

Aziz

[moodz]

What about a DSP?

Could make things easy.

Aziz

I already tried FFT .... because the pulses are broadband ... unlike VLF detectors the energy and phase dispersal is too spread out ... especially on small targets and very weak so poor resolution. Worse the power and phase vectors vary greatly with orientation to coil. Just coil moving across target causes great changes in phase and power with no definite target signature except on quite large targets close to coil.
So presently the design is fully synchronous demodulation which removes more than 60 dB of noise and oversampling extends effective sample bits to 19 ( 14 bit native ADC ) The resulting wave form is passed through 2nd order derivative function to obtain descrimination information and power integration for target volume / range. Alternating polarity Tx waveforms and late sample differencing provide Earth field compensation and reference differential analysis compensates for ground effect. Single and multi pulse waveforms may be changed on the fly ... eg alternating 100us pulse to triplet 60 us pulse every 50 ms ( 50 ms or 20 hz is the low pass cutoff ). This avoids patent trouble as multi-pulse Tx waveform is transmitted and analysed in separate time periods.

If you know of way to apply FFT with sufficient sensitivity then I am interested to learn .. however my experience is that FFT is very poor on weak signals ( small or deep targets ).

moodz

[Tinkerer]

Changed the pulse generator back to 100 Mhz clock ... step size is 10 ns .. 0 to 65535 ( 16 bit control ) or 0 to 655.35 us in .01 us steps.

The sample clock is 1.3 Mhz and the pulse repetition is 196 us or 5.098 Khz .... pretty high for a PI but lots of samples = lots of sensitivity.

Now the question is how many sample points ????

1 sample during transmit.
1 early sample just after fly back
1 mid sample 50 to 100 us
1 late sample at 196 us

How to process ???

moodz

There is really only one way to decide where along the timeline of the cycle to place the sampling spots.
You have to sample every part of the cycle, see what the target and ground response is at each spot, then chose the few best spots, that is the spots that give you the most reliable information about the target and the ground, to take your samples.
You need to do this initial testing, using every possible target size and metal and every possible ground effect. Quite a lengthy procedure really.

It is surprising how moving a sample timing spot by just one or 2 us, can change the effectiveness of the sample.

Then you invert, add, subtract, divide or multiply specific sample groups, to eliminate ground effects, enhance FE recognition or rejection and generally enhance the response of the most desired targets.

I would be willing to do some of these test series for you, but I need to have and use your exact setup, to make sure the results fit precisely your system and methods.

Any change in coil, TX power and duration, front-end circuit, etc. will change the output. However, with the great resources of the FPGA, these changes can be compensated, as long as you know exactly how the desired responses need to be.

Tinkerer

[moodz]

FPGA update

There is really only one way to decide where along the timeline of the cycle to place the sampling spots.
You have to sample every part of the cycle, see what the target and ground response is at each spot, then chose the few best spots, that is the spots that give you the most reliable information about the target and the ground, to take your samples.
You need to do this initial testing, using every possible target size and metal and every possible ground effect. Quite a lengthy procedure really.

It is surprising how moving a sample timing spot by just one or 2 us, can change the effectiveness of the sample.

Then you invert, add, subtract, divide or multiply specific sample groups, to eliminate ground effects, enhance FE recognition or rejection and generally enhance the response of the most desired targets.

I would be willing to do some of these test series for you, but I need to have and use your exact setup, to make sure the results fit precisely your system and methods.

Any change in coil, TX power and duration, front-end circuit, etc. will change the output. However, with the great resources of the FPGA, these changes can be compensated, as long as you know exactly how the desired responses need to be.

Tinkerer

Ok I will make up 4 sample points for each pulse period. There will be two types of pulse period. One with a single pulse ( fully variable ) and a doublet or triplet pulse period ( fully variable )
This will be upto 8 sample points in total across both pulse periods.
The sample controls will be a 16 bit value to set sample delay ( 10 ns resolution ) and sample duration or ADC count ( number of ADC values to sample.)

moodz

[Aziz]

Hi Moodz,

I would suggest to use integrated samples over a time window rather than just sampling the signal values. Integrators have an inherent low pass filter characteristics, which reduce high frequency noise automatically. The output of the integrators should be sampled instead.

The FPGA is well designed to implement several integrating ADC's. Let's assume, your conversion time is 1 ms and your ADC clock is running at 200 MHz.
For one ADC cycle there will be 200 000 clocks
n ADC bits = ld (200 000) = 17.6 bits (max. ADC resolution)


So you would need a precision current source (voltage ramp generator at charging capacitor), a fast comparator and a 18-20 bit counter each ADC channel. The µC/DSP could read the channels and process it.

You can get rid of the external ADC. The FPGA could do it with ease.
Aziz

[moodz]

Hi Aziz ... thanks for that very good idea ... the FPGA input can digitise analogue signals with minimal external components like this ....

WP-Creating_An_ADC_Using_FPGA_Resources.pdf


moodz

[Tinkerer]

Hi Moodz,

I would suggest to use integrated samples over a time window rather than just sampling the signal values. Integrators have an inherent low pass filter characteristics, which reduce high frequency noise automatically. The output of the integrators should be sampled instead.

The FPGA is well designed to implement several integrating ADC's. Let's assume, your conversion time is 1 ms and your ADC clock is running at 200 MHz.
For one ADC cycle there will be 200 000 clocks
n ADC bits = ld (200 000) = 17.6 bits (max. ADC resolution)


So you would need a precision current source (voltage ramp generator at charging capacitor), a fast comparator and a 18-20 bit counter each ADC channel. The µC/DSP could read the channels and process it.

You can get rid of the external ADC. The FPGA could do it with ease.
Aziz

Aziz,

I have been using the circuit below (found on the datasheet) for the S&H of the TINKERERS IB-PI. I wonder how it compares with an ordinary Integrator.
Would you be so kind and give your opinion?

Tinkerer