TGSL Tuning & troubleshooting

[Mullihaka]

How about capacitor selection in you project. Since it works better on a separate P.S. maybe look at what you are using for polarized caps?? Can you post what you are using and maybe we can compare the ripple specs?

Electrolytics are just off the shelf from the local shop; they are from Lelon. I can find the manufacturer's home page, but that's where the track ends; there's so many types listed. The nF range bypass caps are ceramic.

The additional 330nF caps I scattered around the + and - rails are SMD's I bought some time ago. They were quite efficient in killing the spikes.

It's evident I have overlooked the ESR (effective series resistance) of the elctrolytics. I have plenty of SMDs to replace them, but there's not enough ground around to connect them. I wish I made the PCB two sided, the component side being solid ground plane.

I haven't found the IC recommended several messages above; I would replace the TR7/8 circuit with that at once.

[johnsmith77]

I haven't found the IC recommended several messages above; I would replace the TR7/8 circuit with that at once.

I suggested you 7660 as i found it in TGSL thread, but now i am not shure it was a good idea.

Some bad info found here: http://www.geotech1.com/forums/showt...onic#post85360
: "Because of 7660 DC converter, there's a lot of noise at the output of preamp."

"7660 is source of many problems"

Also as i remember Ivoconic did not like 7660.

[simonbaker]

I am interested in seeing what it will do for a TGSL that is already getting good depth.

Winter weather is about here so I hope to be back to experimenting with this soon.

Jerry

I agree, good idea -- we'll all learn from your experiments.

Cheers,

-SB

[simonbaker]

Simon, can you elaborate on the conditions required to forward bias the JFet junction?
I have read your post in the past regarding this but have largely ignored it because I have not had any issues.. Are we speaking of badly nulled coils to cause this?

Don

Yes, although I don't know if every coil is susceptible to it.

Basically, you've seen that the null phase is different depending on which side of the null minimum you choose. With one of the phases, the DISC (or GB) control sometimes can cause a large negative DC voltage on capacitor C12/C15 at some point in its range.

If the voltage goes below about -.5 volts, then the sync pulse, when up to ground voltage, can forward bias the JFet gate-to-source junction. So it seems to me a good idea to make sure that doesn't happen when you null your coil.

The forward biasing is not totally disasterous, but degrades the performance I think. Sometimes it only happens at one extreme of the DISC control and is not a big issue.

That's my take on it. I generally check the voltages on C15, C12 over the range of the DISC pot after nulling.

-SB

[simonbaker]

I agree with this: the target phase is not affected by your null signal phase.
Lets say null phase= ph0
Target phase= phtarget
Total phase = ph0 +- phtarget (+ or - depends on target.)
I think ph0 is important as ph0 affects rx/geb sampling phase and rx/disc sampling phase. Geb phase can be trimmed, but disc not.
Maybe i am not correct, it is important understand how it works for future designs.

The total phase doesn't really matter for detecting targets, because the null phase only contributes a constant voltage which does not propagate through the filter/amplifier section. So the DISC pot always is used to track the target phases and should not be affected by the null phase or the total phase for the purpose of discriminating targets.

Does that make sense?

-SB

[turtlebowl]

7660

Just read the 7660 threads. They center around the 7660 being used in a different detector and those discussing the topic are divided it seems.
As the thread is a few years old I am wondering if anyone has done any more experimenting/testing with the 7660 to determine if it actually causes any negitive effects in the Tesoro circuits such as noise or lag.
I really like the simplicity of the 7660 as a combo neg supply source and audio tone generator and would like to use it in a design similar to the Tesoro.
Any more recent thoughts on the chip??
TB

[johnsmith77]

The total phase doesn't really matter for detecting targets, because the null phase only contributes a constant voltage which does not propagate through the filter/amplifier section. So the DISC pot always is used to track the target phases and should not be affected by the null phase or the total phase for the purpose of discriminating targets.

Does that make sense?

-SB

Hm, then i should ask is geb and disc sampling pulse phase important?
There was discussed that GEB sampling should be at the zero crossing. Seems it is important.
Is it affected by null phase? Seems yes. So i make a conclusion
Please correct me if i am wrong again

[Dennis the Mennis]

(Re-) Define Coil 'Nulling' - Adjusting ?

Originally Posted by dfbowers
Simon, can you elaborate on the conditions required to forward bias the JFet junction?
I have read your post in the past regarding this but have largely ignored it because I have not had any issues.. Are we speaking of badly nulled coils to cause this?

Don

Yes, although I don't know if every coil is susceptible to it.

Basically, you've seen that the null phase is different depending on which side of the null minimum you choose. With one of the phases, the DISC (or GB) control sometimes can cause a large negative DC voltage on capacitor C12/C15 at some point in its range.

If the voltage goes below about -.5 volts, then the sync pulse, when up to ground voltage, can forward bias the JFet gate-to-source junction. So it seems to me a good idea to make sure that doesn't happen when you null your coil.

The forward biasing is not totally disasterous, but degrades the performance I think. Sometimes it only happens at one extreme of the DISC control and is not a big issue.

That's my take on it. I generally check the voltages on C15, C12 over the range of the DISC pot after nulling.

-SB

Hi ,

I think this is one of the walls I ran into ...

After been pointed in the right direction by someone ( thnx -SB ), a lot of pieces of the puzzle fell at their place .

Perhaps we should (re-) define the 'nulling' procedure or should we even better speak of 'Coil Adjusting' :


"Adjust the coils in such a way where we achieve the 'lowest' residual voltage but where the voltage on C12/C15 don't go below -0,5V. "


So it not necessary to get the lowest residual voltage. ???


This is the procedure I potted my coils and it seems to work.

I think once again the shielding of the coils can be of a great influence of this procedure.

Where the kitchen AL foil did not work for me , the Mylar foil I used ( the 'thicker' Mylar shielding out of a VGA cable ) worked a lot better

The thinner Mylar shield Don used of his rescue blanket is perhaps even better , I never tried it (yet).


Could this be the explanation why Don didn't have to check the voltages on his capacitors ?


It acts as an 'ideal' set of coils , like unshielded (test)coils :

- The overall minimum residual voltage is much lower compared to AL foil shielded coils(don't mind the C12/15 voltages yet )

-The phase shift seems the act more ideal , allthough this does not seem to care that much

- The 'ideal' voltage set for the capacitors C12/C15 can be achieved with a lower residual voltage compared to Al foil shielded coils

These are a lot remarks and comments made by members building the TGS / TGSL / IGSL like described as above and below:

- " Why is my residual voltage not that low as others describe .... " ( shielding issues ? )
- " Why is my TGSL not working at the lowest residual voltage..." ( the C12/C15 voltage way below -0,5V ? it caused on my pcb lots of noise when the voltage dropped below -0,5V )
- "why don't I get the 'ideal' -20 degrees shift ..." ( shielding issues ? )

Perhaps some more to thinker about or needs some more experimenting ?


kind regards

Dennis the Mennis

[johnsmith77]

If the voltage goes below about -.5 volts, then the sync pulse, when up to ground voltage, can forward bias the JFet gate-to-source junction.

-SB

About forward biasing.

There can be mistake. At this point measurements should be done according to ground point?
I think NO. Should be measured according to source pin Tr4, or Tr5.
Measuring S-G i have about -5V. S-D is not so negative (i don't remember how big, but very low). So i can't achieve forward biasing.
As i understand forward biasing there will be if S-G goes to positive for N Fet transistor.
And if we will measure according to ground point, we will get some confusion here. I am not sure 100%, but 99%

[simonbaker]

About forward biasing.

There can be mistake. At this point measurements should be done according to ground point?
I think NO. Should be measured according to source pin Tr4, or Tr5.
Measuring S-G i have about -5V. S-D is not so negative (i don't remember how big, but very low). So i can't achieve forward biasing.
As i understand forward biasing there will be if S-G goes to positive for N Fet transistor.
And if we will measure according to ground point, we will get some confusion here. I am not sure 100%, but 99%

Hi johnsmith77!

It is good to question all wisdom because often wrong -- especially mine.

Here is how I see it -- the sync pulse at the JFet Gate goes from approximately -5 volts to zero volts (ground) as a square wave. In our circuit, (with N Channel JFet) when Gate is at zero volts, the JFet turns on. When it is at -5 volts, the JFet turns off. This assumes that the Drain and Source voltages are not far from ground voltage.

When the JFet is turned on, the Drain and Source voltages are approximately equal because the JFet channel is low resistance -- current can flow in either direction, depending on which is higher voltage, the Drain or Source. That is how we charge and discharge capacitors C12, C15.

But if our null signal is of a certain phase, the JFet will turn on when the output of the LF353 is at the negative half of the sinusoid. Depending on your null signal, it could be between -1 and -2 volts. This would cause the JFet to become forward biased, because when the Gate is at zero volts, the Drain/Source is between -1 and -2 volts -- the Gate is more positive than the Drain/Source.

This can be tolerated for small signals perhaps. However, I have seen the JFet become forward biased in some of my circuits when my null signal phase was extreme and I turned the DISC pot to where it caused the above mentioned effect. The Gate voltage became distorted and I think the sync pulse was charging the capacitors.

So I think it is recommended that we make sure our null signal phase does not cause forward biasing of the JFets. If it is only a little bit, it is probably OK, but something to look out for.

-SB

[simonbaker]

Hm, then i should ask is geb and disc sampling pulse phase important?
There was discussed that GEB sampling should be at the zero crossing. Seems it is important.
Is it affected by null phase? Seems yes. So i make a conclusion
Please correct me if i am wrong again

My answer is a little complicated.

Qiaozhi and I had long discussion about this, concerning how to set the null phase for practical ground balancing.

Qiaozhi used the assumption that soil (and ferrite) would amplitude-modulate whatever null signal you achieved without affecting its phase. Therefore, he felt it was practical to choose a null phase (by adjusting the coil overlap) such that the GEB sampling would center on the zero crossing when the GB pot was in its middle position. This would allow you the best range of adjustment of the GB pot for different ground conditions. I agree this makes sense based on those assumptions.

However, since then, I have been thinking that the null signal may consist of several components (for example, magnetic and capacitive coupling of the coils), and only some components are affected by soil/ferrite. I call the components that are affected by soil/ferrite the "magnetic" components, and the other part the "non-magnetic" components. Of course it may be much more complicated than that, but I will start with that model and hopefully do some experiments.

But my main feeling is this: the phase of the magnetic components of the null signal are mostly fixed by the design of our metal detector, including the shields we choose and how close the RX resonant circuit is to the TX oscillator frequency; and also which side of the null minimum we choose. Even though we can change the total phase of the null signal continuously by shifting our coil overlap, we are not really moving the phase of the magnetic components significantly (until we flip to the other side of the null) -- therefore, our GB pot will always cancel the soil/ferrite signal at roughly the same point regardless of how we shift the null phase on one side of the minimum.

I think it may also be true that when we flip the null phase to the opposite side of the minimum, the zero crossing of the magnetic components will be not far from the zero crossing at the other side of the minimum (although it will cross in the opposite slope), so our GB pot setting for ground balancing would still be similar.

So my conclusion is that yes, the GB pot setting should center on the zero crossing of something, but not necessarily the total null signal. Rather, it should center on the zero crossing of the "magnetic" portion of the null signal. This is practically achieved by waving ferrite across the coils and stimulating the magnetic portion of the null signal, and adjusting the GB pot to cancel that signal (in my opinion).

-SB

[simonbaker]

Hi ,

I think this is one of the walls I ran into ...

After been pointed in the right direction by someone ( thnx -SB ), a lot of pieces of the puzzle fell at their place .

Perhaps we should (re-) define the 'nulling' procedure or should we even better speak of 'Coil Adjusting' :


"Adjust the coils in such a way where we achieve the 'lowest' residual voltage but where the voltage on C12/C15 don't go below -0,5V. "


So it not necessary to get the lowest residual voltage. ???


This is the procedure I potted my coils and it seems to work.

I think once again the shielding of the coils can be of a great influence of this procedure.

Where the kitchen AL foil did not work for me , the Mylar foil I used ( the 'thicker' Mylar shielding out of a VGA cable ) worked a lot better

The thinner Mylar shield Don used of his rescue blanket is perhaps even better , I never tried it (yet).


Could this be the explanation why Don didn't have to check the voltages on his capacitors ?


It acts as an 'ideal' set of coils , like unshielded (test)coils :

- The overall minimum residual voltage is much lower compared to AL foil shielded coils(don't mind the C12/15 voltages yet )

-The phase shift seems the act more ideal , allthough this does not seem to care that much

- The 'ideal' voltage set for the capacitors C12/C15 can be achieved with a lower residual voltage compared to Al foil shielded coils

These are a lot remarks and comments made by members building the TGS / TGSL / IGSL like described as above and below:

- " Why is my residual voltage not that low as others describe .... " ( shielding issues ? )
- " Why is my TGSL not working at the lowest residual voltage..." ( the C12/C15 voltage way below -0,5V ? it caused on my pcb lots of noise when the voltage dropped below -0,5V )
- "why don't I get the 'ideal' -20 degrees shift ..." ( shielding issues ? )

Perhaps some more to thinker about or needs some more experimenting ?


kind regards

Dennis the Mennis

Hi DtM:

I basically agree with those ideas and questions. I think the type of shield can affect the null phase and make it hard to achieve a "satisfying" null phase. I also agree it may be true that the "minimum" null voltage is not the one we want, although there can be a number of practical reasons for that. But even in a pure sense, it may be true that we want to minimize the "magnetic component" of the null, not the total null signal.

I'm trying to come up with a math model of these ideas that we can test experimentally. (Don't hold your breath...). I should also say that these thoughts are specific to the TGS/TGSL design and maybe are different for other metal detectors.

-SB

[Wiltran]

Hi DtM:

I basically agree with those ideas and questions. I think the type of shield can affect the null phase and make it hard to achieve a "satisfying" null phase. I also agree it may be true that the "minimum" null voltage is not the one we want, although there can be a number of practical reasons for that. But even in a pure sense, it may be true that we want to minimize the "magnetic component" of the null, not the total null signal.

I'm trying to come up with a math model of these ideas that we can test experimentally. (Don't hold your breath...). I should also say that these thoughts are specific to the TGS/TGSL design and maybe are different for other metal detectors.

-SB

I agree with the min. null voltage may not be the one we want. i think it was Jerry , who ran a computer model that showed an optimal range some what above 0V. The last DD coil I made , I spent more time getting exact TX freq, and Rx capacitor matching to get good 20 deg phase differential. the performance is very good, ground balance perfect and discrimination very good. This was on IDX, but i'm sure TGSL is the same.

[johnsmith77]

My answer is a little complicated.


-SB

I think phase is not important, if we accept this:
Instead some metals are discriminated at disc pot position e.g 4,
having different null phase shift, we achieve the same discrimination at disc pot position 3 or 5,
depending how bigger or lower null phase we’ll have. That’s not affect tgsl very much in this way.


Is it correct?

[eduardo1979]

My TGSL-EDU 2 TON
http://www.youtube.com/watch?v=fiDkh...el_video_title