Simple MicroProcessor PI Idea

[rickodetrader]

Hi All,

The penny is starting to drop thank goodness. But bear with me I would like to get this out! A bunch of you will probably be like: "I know this already!!!"

The following is my arrival at a bugwhiskers type idea for a multiple sample and hold type PI metal detector. The reason for doing it this way is the common 8-bit processors available have slow internal Analog to Digital conversion capabilities. Even though faster external ADCs can sample fast the time to export to the micro in real time is relatively slow.

After looking thru several PI circuits: Hammerhead, SMPI Pro etc. which use an analog integrator (differential amplifier)there are of course two inputs with the difference being the output. The current sample signal comes in the + terminal of the op amp and the capacitor "averaged" sample signal is fed into the - terminal. To my way of understanding the averaging is accomplished by storing the previous sample voltages in a capacitor. We measure the difference to this average with the integrator op-amp (differential amp). The charge rate of the capacitor can be controlled by resistors proceeding the cap usually after a 4066 switch. There is a resistor in parallel to discharge the cap so after the high signal of a target has passed the cap is pulled back to it's "no signal present" voltage within a small amount of time.

Why can't we do this with a microprocessor?

For simplicity's sake (i'm sure there is a better solution!! ie. multiplexer) we have a 4066 (quad bilateral switch) with all the gates attached to 4 digital output pins of a micro for gate timing control. A buffer amp (gain 1) is after the preamp(s). Buffer amp is able to drive capacitive loads better so as not to load preamp. All the inputs of the switches are attached to the output of the buffer amp. Each output from the different switches that make up the 4066 are attached to 4 different capacitors which store the sample voltages.

So using the micro we turn on the FET for x amount of time (Tx pulse) then turn it off after the specified number of microseconds. (Rx) We wait (dead time) then switch on gate1 to do sample1 -> cap1 is charged from buffer amp, then switch off gate1, wait a number of microseconds turn on gate2 -> cap2 is charged with sample2 voltage then switch gate 2 off. Process repeats for cap3 and cap4. Since simple switching (digital outs on a uC) is accomplished usually within 1-4 clock cycles it is not processor intensive, laggy etc allowing us to direct the preamp output to be stored quite quickly before our beloved signal has decayed to zero.

After all the samples are taken then we actually do the time consuming chore of reading the individual cap values into the microprocessor for processing when time isn't at a premium, do our calculations, alter audio output, update screen whatever.

Now I haven't tested this but I think it will work. Tx time Dead time, sample length, sample delays are all easily configurable and savable with a micro allowing for great flexibility. I know it is somewhat reinventing the wheel

A few things I'm not real sure about are:

1. What value capacitor would be sufficient? 100n?

2. How long would the sample time (ie. the time gate is held on) need to be to charge the capacitors? Would 1 uS be sufficient to charge a eg. 100n cap?

3. Would there be much natural discharge of the caps in the 50-100 uS before we start reading values into the micro?

What do you think? Am I on to something here...?

[TH Jim]

Interesting - are you going to prototype it?

Regards, Jim

[6666]

the 4066 are attached to 4 different capacitors which store the sample voltages

Check out the blind squirrel and what it does with caps, sounds like your idea is similar.
It only uses one cap.

http://oldradiobuilder.com/mdetsp.html

[Qiaozhi]

Check out the blind squirrel and what it does with caps, sounds like your idea is similar.

http://oldradiobuilder.com/mdetsp.html

What rickodetrader is proposing is to take multiple samples along the decay curve, in a similar manner to bugwhiskers' idea. The blind squirrel does not have that feature, as it only takes one sample.

If you look carefully at U4 (4066B), you will see that two of the analog gates are unused, and the other two are connected in series. There appears to be some charge shuttling going on between C14 (1nF) and C15 (10nF) - [what the purpose of this is I'm not sure, unless it's a switched capacitor filter] - but there's still just one sample being taken. The text only describes U4 as "the sample circuit".

[6666]

Hi Qiaozhi
When I saw the questions that rickodetrader was asking about
"Would there be much natural discharge of the caps" and values, etc.

The simple blind squirrel schematic came to mind, I may be wrong, its a while since I studied the schematic, and was discussed on another forum, but I was under the impression from the very basic circuit description on the website, that Cap14 or Cap15 stored a voltage charge, which varied with a target, this charge was then monitored by U5A, U5B etc etc.

All I was trying to point out to Rick in not so many words, was if C14 or C15 work this way in the simple blind squirrel schematic, then there is a good chance using multiple caps in the way he describes with multiple samples etc, has a good chance of working.

6666

[jon-ecm]

Interesting idea - Would love to see an implementation and hear what kind of results you get.
Personally I'm crazy about high powered micros and ultrafast hi-resolution adc's like I've used on the xpi, High speed dsp microcontrollers arn't expensive with 400mhz 8 threaded xmos processors starting at $7 in single qty's; it will quickly be cheaper than analog stuff...

Just my 2c

__________________________________________________ _____________________________
400MHZ 8 Threaded MCU, 16 bit 2MSPS ADC, it's all about depth... http://www.miymd.com/index.php/projects/xpi/

[rickodetrader]

Hi Guys,

Yes I hope to get a prototype happening soon so with a bit of luck that won't take too long.

jon-ecm: I would like to end up doing something with higher power but for now this is what I have to work with. Have been following yourself and hdphilip is up to something similar on here. Seems very promising!!!

Started working on a schematic and board in Eagle so I'll post what I come up with once it is somewhat working correctly. Probably whack something together on a breadboard first and hook it to my arduino for some initial testing then go from there.

Fingers crossed

[hdphilip]

hey rick,

sounds like a fun project, looking forward to your postings

Philip

[Carl-NC]

Rick,

What you propose isn't too far from what's been done. Several PI and VLF detectors use multiple parallel sampling integrators which are then run to a common ADC and read in at leisure. The twist that you seem to propose is to replace the sampling integrators with a sample-and-hold, and do the integration in software.

Sure, you can do that. A couple of years ago I built a PI detector in which I could switch between using a SHA and a sampling integrator; I found that with the latter it was easier to get better performance, so I ditched the SHA. But I was only looking at 2 sample points, so the circuitry was manageable.

If you want to look at lots of sample points, then the SHA approach is simpler. But I would then argue that you would be even further ahead to solve the ADC data transfer issue. And, with newer ADCs and micros, it's probably already solved. You should be able to easily capture 16-bit signals at 2us apart, maybe better. Use the leisure time for processing those signals.

- Carl

[Davor]

IMHO 16 bit is far too much. Adding multiple samples (instead of averaging) would get you there even with less bits at ADC. True benefit of digital approach is FIR nature of such process that is not prone to silly delays of FIR filtering. Some detectors out there have ridiculous delays.

Comparing SAH and integrator, the former is in disadvantage as being able to store only a preceding pulse charge, while integrator holds many more. I believe combining the two will be much better than either of them alone.

[Carl-NC]

If you are running nothing but a preamp and ADC, then even 16 bits may be borderline. I have a 10-bit direct-sampled PI detector (MAX410 + PIC12F1840) which is OK for a pinpointer or a security wand, but woefully insufficient for ground detecting. I expect 12 bits would still be weak, and 16 bits might work pretty good. An amp+integrator with 12 bits might also work pretty good. Not sure what you mean by combining a SHA and integrator; the sampling integrator used on most PI designs is effectively that.

- Carl

[Davor]

More or less. Integrator is an IIR component, while SAH isn't. Point is that in usual PI solution you are feeding an integrator sharp pulses with long pauses and you can't play with history pulses at all. SAH keeps a sampled voltage constant till the next pulse, thus extending pulse energy. In effect a unity gain SAH provides effective gain of pause duration/pulse duration, which is quite significant with PI. (In CDMA similar process is called "processing gain".) Additionally, your ADC can take its time, and FIR integration can be easily done in digital domain as, say moving average.

In case you use, say, 12 bit ADC, and instead of average you just add 16 samples you are in a 16 bit ballpark (just like sigma delta does). Noise will take care of dithering etc.

[Aziz]

...
In case you use, say, 12 bit ADC, and instead of average you just add 16 samples you are in a 16 bit ballpark (just like sigma delta does). Noise will take care of dithering etc.

2 samples = half bit
4 samples = 1 bit
16 samples = 2 bit

It would end with 14 bit only.

[Carl-NC]

More or less. Integrator is an IIR component, while SAH isn't. Point is that in usual PI solution you are feeding an integrator sharp pulses with long pauses and you can't play with history pulses at all. SAH keeps a sampled voltage constant till the next pulse, thus extending pulse energy. In effect a unity gain SAH provides effective gain of pause duration/pulse duration, which is quite significant with PI. (In CDMA similar process is called "processing gain".) Additionally, your ADC can take its time, and FIR integration can be easily done in digital domain as, say moving average.

There are advantages in having the raw samples to play with in software, but there are drawbacks, too. A significant advantage of the integrator is that it averages noise even over the sample width* of an individual sample, whereas the SHA does not. I found in my SHA/integrator design that the SHA method was quite a bit noisier, requiring a whole lot more work in software to clean up. And, with detectors, you are limited in the amount of post-processing because it induces noticeable audio delays.

In case you use, say, 12 bit ADC, and instead of average you just add 16 samples you are in a 16 bit ballpark (just like sigma delta does). Noise will take care of dithering etc.

I'm using a 10-bit ADC and 64 samples in my averaging, for an effective 13 bits (Aziz is correct). And it's not very good. I have a new design in layout that increases this considerably... it's an expensive way to end up with the same performance as a cheap-n-dirty integrator but, as I said, there are advantages.

- Carl

*It's interesting even to play with sample width.

[Davor]

Yeah, OK, I did not play with ADC/DAC for some time now and I forgot a detail or two.

I still don't quite understand the big difference in noise you mention with integrator against SAH. Integration during sample width seem incredibly simple to achieve by playing with source impedance and sampling capacity, so there should not be that much of difference in noise either. The end result is a signal that floats below, say, 20Hz and FIR seem a logical choice for faster response.

I'll surely give this a serious thought

Anyway, my recent crash is a blind squirrel and the way its made