Concept Design

[ivconic]

I have a question about the RX coil:
For a differential input, we can use a center tapped RX coil or a floating RX coil. I simulated both and do not get much difference.
How does that look with the noise analysis?
About the “hot ground”:
I remember in Venezuela, there were areas where I had to sweep the coil at a height of about 12” above the ground not to get the detector saturated.
Some of the ground was magnetic, but there also was a certain amount of salt at some places. There was a lot of Manganese in the rocks and ground. Manganese oxidates brown or black, looks a lot like iron oxide. There is also a lot of bauxite.
So, all in all, without having any actual numbers, I feel we need to have a relatively large dynamic range. Using +/- 5V and an attenuator will help, while still using a gain of maybe 500 to 1000 on the AFE.

I have a similar situation on about 30% of my sites here.
It would be very interesting to check how the detector would behave at night.
Have you ever tried it?

[Tinkerer]

I have a similar situation on about 30% of my sites here.
It would be very interesting to check how the detector would behave at night.
Have you ever tried it?

At night?
At night I got bitten and stung by a zillion blood sucking insects. I drove over an alligator with the pickup. I stepped on a 8 foot snake. I learned to tell the size of an alligator by the distance between its eyes. I learned to tell the kind of animal by the color of the reflection of the eyes with a flashlight. Alligator eyes reflect red. Deer eyes reflect white. Jaguar eyes scream get the hell out of here. Only a fool would go metal detecting at night in the jungle.

[ivconic]

At night?
At night I got bitten and stung by a zillion blood sucking insects. I drove over an alligator with the pickup. I stepped on a 8 foot snake. I learned to tell the size of an alligator by the distance between its eyes. I learned to tell the kind of animal by the color of the reflection of the eyes with a flashlight. Alligator eyes reflect red. Deer eyes reflect white. Jaguar eyes scream get the hell out of here. Only a fool would go metal detecting at night in the jungle.

That's exceptional case you got there.
The point of the whole story is to establish whether there are significant differences in soil properties during the day and during the night.

[ivconic]

That's exceptional case you got there.
The point of the whole story is to establish whether there are significant differences in soil properties during the day and during the night.

I am sure you can put it in simulator and get 101% accurate results.

[Carl-NC]

The point of the whole story is to establish whether there are significant differences in soil properties during the day and during the night.[/FONT]

It is my understanding that magnetic susceptibility decreases with increasing temperature. So at night, plain mineralized soil may seem stronger, meaning you may have to reduce sensitivity.
But usually the bigger problem is magnetic viscosity, which is worse with increasing temperature so night hunting may exhibit less ground noise.

[Carl-NC]

I have a question about the RX coil:
For a differential input, we can use a center tapped RX coil or a floating RX coil. I simulated both and do not get much difference.
How does that look with the noise analysis?
About the “hot ground”:
I remember in Venezuela, there were areas where I had to sweep the coil at a height of about 12” above the ground not to get the detector saturated.
Some of the ground was magnetic, but there also was a certain amount of salt at some places. There was a lot of Manganese in the rocks and ground. Manganese oxidates brown or black, looks a lot like iron oxide. There is also a lot of bauxite.
So, all in all, without having any actual numbers, I feel we need to have a relatively large dynamic range. Using +/- 5V and an attenuator will help, while still using a gain of maybe 500 to 1000 on the AFE.

A CT coil may increase noise. With a non-CT coil the vn1 term is due to a 2k resistor current noise that is coherent between the 2 input stage so you have to double its effect. A CT coil splits the input resistor so now each opamp sees a 1k resistor current noise (2x) but they are incoherent so they sum as sqrt-sum-of-squares. The overall effect is a higher vn1 noise by sqrt(2). The original analysis suggests 22 LSBs of noise, a CT coil comes out to 27.5 LSBs. This is a chicken scratch analysis so I don't offer a guarantee of accuracy.

One thing I'm looking at is ADC full-scale range. some go up to 10V and even 12V. The bigger the better, as long as you can get a suitable opamp to drive it.

So far I am with Moodz on the TX slope. I am still not seeing anything that tells me it must be dealt with in analog and, like him, I am skeptical that any solutions would be all that effective. In multifrequency VLF designs a (voltage) square wave drive on the TX produces a square wave voltage on the RX for ground signals. You simply design the AFE for whatever dynamic range is needed to deal with it. I can't imagine that we could ever be able to run a gain of 1000 or even 500. I expect 100 or so. If someone has done an analysis that clearly shows the problem and ways to deal with it, please post it.

On coils, I have no preference but it obviously has to be induction balanced. Usually I start with an OO coil on the bench because it's simple.

[ivconic]

It is my understanding that magnetic susceptibility decreases with increasing temperature. So at night, plain mineralized soil may seem stronger, meaning you may have to reduce sensitivity.
But usually the bigger problem is magnetic viscosity, which is worse with increasing temperature so night hunting may exhibit less ground noise.

And the "invisible" coins during the day all of the sudden become "visible" during the night.
At least that's my personal experience, repeated so many times so far.
Conclusion... if any?

[ivconic]

Any chance any sooner to see concrete schematics, drawn in schematic capture sonftware...?
It's kinda weird to read so much about coils, gains, noises... tones of spice simulations... and no real piece of schematic at all!??
Don't offer parts of schematic from spice simulators; IT IS NOT schematic!

[Carl-NC]

And the "invisible" coins during the day all of the sudden become "visible" during the night.
At least that's my personal experience, repeated so many times so far.
Conclusion... if any?

I would speculate that they are getting masked by viscous responses. Just a guess. You might be able to determine this by using a true all-metal threshold mode.

Any chance any sooner to see concrete schematics, drawn in schematic capture sonftware...?
It's kinda weird to read so much about coils, gains, noises... tones of spice simulations... and no real piece of schematic at all!??
Don't offer parts of schematic from spice simulators; IT IS NOT schematic!

The differential preamp was posted in the TX thread, I don't see anything much better than that. Otherwise, the AFE needs some minor low-pass filtering and an ADC. Power supply is TBD but won't be esoteric. TX has also been posted. There isn't much more to it than that other than micro, audio driver, and display. But, yes, when I feel like all the problems are either solved or at least understood then I will put together a formal schematic. No need to jump ahead until we're ready.

[moodz]

A CT coil may increase noise. With a non-CT coil the vn1 term is due to a 2k resistor current noise that is coherent between the 2 input stage so you have to double its effect. A CT coil splits the input resistor so now each opamp sees a 1k resistor current noise (2x) but they are incoherent so they sum as sqrt-sum-of-squares. The overall effect is a higher vn1 noise by sqrt(2). The original analysis suggests 22 LSBs of noise, a CT coil comes out to 27.5 LSBs. This is a chicken scratch analysis so I don't offer a guarantee of accuracy.

One thing I'm looking at is ADC full-scale range. some go up to 10V and even 12V. The bigger the better, as long as you can get a suitable opamp to drive it.

So far I am with Moodz on the TX slope. I am still not seeing anything that tells me it must be dealt with in analog and, like him, I am skeptical that any solutions would be all that effective. In multifrequency VLF designs a (voltage) square wave drive on the TX produces a square wave voltage on the RX for ground signals. You simply design the AFE for whatever dynamic range is needed to deal with it. I can't imagine that we could ever be able to run a gain of 1000 or even 500. I expect 100 or so. If someone has done an analysis that clearly shows the problem and ways to deal with it, please post it.

On coils, I have no preference but it obviously has to be induction balanced. Usually I start with an OO coil on the bench because it's simple.

NXP semi have a 24 bit ADC that does +\-25 volts direct .... but ENOB decreases with sample rate ( to be expected ).

[moodz]

Any chance any sooner to see concrete schematics, drawn in schematic capture sonftware...?
It's kinda weird to read so much about coils, gains, noises... tones of spice simulations... and no real piece of schematic at all!??
Don't offer parts of schematic from spice simulators; IT IS NOT schematic!

..it will get there .. no point publishing schematics of a moveable feast. Some projects are designed in a cathedral and some in a bazaar .... I am more the walk around the bazaar and change my mind 20 times but I will go back to the best shops.
In the cathedral its all done by the numbers and everyone wearing strange clothes.

Stuff is happening .. I have dug out my FPGA bread board and it has a 2.5 MSPS AD7760 ADC on it ... I have already tested the CC transmitter on a VLF coil and it seems to work fine... but obviously will need DSP .. I already have the HDL code for the ADC to talk to the FPGA.

From a modular point of view it is coming together and everything is translatable to different hardware if needs be.

Once the building blocks are tied together the hardware can be finalised.

moodz

[moodz]

.. and below is the HDL code for getting data out of the AD7760 and into memory inside the FPGA.

FPGA guys will know that this code can be easily ported to just about any FPGA.

and for you Ivconic .. you will be reassured to know that HDL can be automatically converted to a schematic if you want to view a ( logic ) circuit diagram.

moodz

----------------------------------------------------------------------------------
-- Company: beepstick
-- Engineer: pm
--
-- Create Date: 11:26:24 05/04/2020
-- Design Name:
-- Module Name: AD7760 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

--PPI SIG AVNET
--1 GND
--2 +5V
--3 +3.3V
--4 C4
--5 A14
--6 MCLK B14
--7 A13
--8 DB0 D13
--9 DB1 C13
--10 DB2 C12
--11 DB3 A12
--12 DB4 D11
--13 DB5 B12
--14 DB6 C11
--15 DB7 A11
--16 DB8 D10
--17 DB9 A10
--18 DB10 E10
--19 DB11 A9
--20 DB12 D9
--21 DB13 C9
--22 DB14 C8
--23 DB15 A8
--24 CS E7
--25 RD/WR B8
--26 D8
--27 A7
--28 D7
--29 DRDY C7
--30 C6
--31 SYNC A6
--32 C5
--33 RESET B6
--34 D4
--35 GND A5
--36 B4
--37 GND E13
--38 D3
--39 GND GND
--40 GND GND




entity AD7760 is
Port ( AD7760_D : inout STD_LOGIC_VECTOR (15 downto 0);
AD7760_RW : out STD_LOGIC;
AD7760_CS : out STD_LOGIC;
AD7760_DRDY : in STD_LOGIC;
AD7760_RESET_O : out STD_LOGIC;
AD7760_RESET_I : in STD_LOGIC;
AD7760_SYNC_O : out STD_LOGIC;
AD7760_SYNC_I : in STD_LOGIC;
AD7760_CLK : in STD_LOGIC;
AD7760_MSW : out STD_LOGIC_VECTOR (15 downto 0);
AD7760_LSW : out STD_LOGIC_VECTOR (15 downto 0);
AD7760_DOUT_RDY : out STD_LOGIC;
AD7760_DIN : in STD_LOGIC_VECTOR (15 downto 0);
AD7760_DIN_RDY : out STD_LOGIC;

AD7760_DATA24 : out STD_LOGIC_VECTOR (23 downto 0);
AD7760_STATUS24 : out STD_LOGIC_VECTOR (7 downto 0);
AD7760_SMPL_COUNT : out STD_LOGIC_VECTOR (15 downto 0)
);
end AD7760;

architecture Behavioral of AD7760 is

-- Enumerated type declaration and state signal declaration
type ADC_State is (stStop, stRESET_0, stINIT_0, stINIT_1, stINIT_2, stINIT_3, stINIT_4, stINIT_5, stINIT_6, stINIT_7, stINIT_8, stIDLE, stREAD_0, stREAD_1, stREAD_2, stREAD_3, stREAD_4, stREAD_5);

signal State : ADC_State := stRESET_0;

-- Counter for counting samples
signal count : std_logic_vector (15 downto 0) := X"0000";
signal delay: integer := 50000;
signal long_delay : integer := 1;
signal idle_count: integer := 0;

signal ready : std_logic := '0';



begin

-- process(AD7760_DRDY) is
-- begin
-- if rising_edge(AD7760_DRDY) then
-- count <= std_logic_vector(unsigned(count) + 1);
-- end if;
-- end process;

process(AD7760_CLK) is
begin

if ready = '1' then --make sure sync does not occur before the chip is initialised.
AD7760_SYNC_O <= AD7760_SYNC_I;
else
AD7760_SYNC_O <= '1';
end if;


if rising_edge(AD7760_CLK) then

if AD7760_RESET_I = '1' then
State <= stRESET_0;
AD7760_RESET_O <= '0';
delay <= 50000; -- 1 millisecond for 50 MHZ clock
long_delay <= 1000; --1 seconds counting delay ticks.
ready <= '0';
else



-- operate the delay counter
if delay > 0 then
delay <= delay - 1;
end if;
-- operate the long delay counter
if ((delay = 0) and (long_delay > 0)) then
long_delay <= long_delay - 1;
delay <= 50000;
end if;


case State is

when stStop =>
if AD7760_SYNC_I = '0' then --one ADC run per RX period.
State <= stIDLE; --wait for next sync pulse
count <= X"0000";
else
State <= stStop;
end if;

when stRESET_0 =>
if delay = 0 then
AD7760_RESET_O <= '1';
AD7760_RW <= '1';
AD7760_CS <= '1';
AD7760_DOUT_RDY <= '1';
count <= X"0000";
State <= stINIT_0;
delay <= 50000;
end if;

when stINIT_0 =>
if long_delay = 0 then -- need to wait at least 0.25 seconds for reset chip on AD7760 board
State <= stINIT_1;
end if;

when stINIT_1 =>
if delay = 0 then
AD7760_D <= X"0001"; --set control register 1 address
AD7760_CS <= '0' after 10 ns; --lower the CS line
State <= stINIT_2;
delay <= 5;
end if;

when stINIT_2 =>
if delay = 0 then
AD7760_CS <= '1'; --raise the CS to write the address in
State <= stINIT_3;
delay <= 5;
end if;

when stINIT_3 =>
if delay = 0 then
AD7760_D <= b"0000000000011000"; --set control register 1 data
AD7760_CS <= '0' after 10 ns; --lower the CS line
State <= stINIT_4;
delay <= 5;
end if;

when stINIT_4 =>
if delay = 0 then
AD7760_CS <= '1'; --raise the CS to write the data in
AD7760_D <= X"0002"; --set control register 2 address
State <= stINIT_5;
delay <= 50;
end if;

when stINIT_5 =>
if delay = 0 then
AD7760_CS <= '0' after 10 ns; --lower the CS line
State <= stINIT_6;
delay <= 50;
end if;

when stINIT_6 =>
if delay = 0 then
AD7760_CS <= '1'; --raise the CS to write the address in
State <= stINIT_7;
delay <= 50;
end if;

when stINIT_7 =>
if delay = 0 then
AD7760_CS <= '0' after 10 ns; --lower the CS line
State <= stINIT_8;
delay <= 50;
end if;

when stINIT_8 =>
if delay = 0 then
AD7760_CS <= '1'; --raise the CS to write the data in
State <= stIDLE;
delay <= 5;
end if;

when stIDLE =>
if delay = 0 then
ready <= '1'; --chip is initialised
AD7760_DOUT_RDY <= '1'; -- clear data ready o/p
AD7760_D <= "ZZZZZZZZZZZZZZZZ"; --tristate the data port
if AD7760_DRDY = '0' then --check if data ready from chip
State <= stREAD_0;
AD7760_RW <= '0';
count <= std_logic_vector(unsigned(count) + 1);
delay <= 0;
idle_count <= 100000; --wait 2 milliseconds
else
idle_count <= idle_count - 1;
if idle_count = 0 then --if idle too long
delay <= 50000;
long_delay <= 1000; --1 seconds counting delay ticks.
AD7760_RESET_O <= '0';
ready <= '0';
State <= stRESET_0; --do reset
else
State <= stIDLE;
AD7760_RW <= '1';
end if;
end if;
end if; --delay

when stREAD_0 =>
if delay = 0 then
AD7760_CS <= '0';
State <= stREAD_1;
delay <= 4;
end if;

when stREAD_1 =>
if delay = 0 then
-- read MSW data
State <= stREAD_2;
AD7760_DATA24(23 downto <= AD7760_D;
AD7760_CS <= '1';
delay <= 0;
end if; --delay

when stREAD_2 =>
if delay = 0 then
State <= stREAD_3;
AD7760_RW <= '1';
delay <= 4;
end if; --delay

when stREAD_3 =>
if delay = 0 then
-- assert read for LSW
State <= stREAD_4;
AD7760_RW <= '0';
delay <= 0;
end if; --delay

when stREAD_4 =>
if delay = 0 then
AD7760_CS <= '0';
State <= stREAD_5;
delay <= 4;
end if;


when stREAD_5 =>
if delay = 0 then
-- read LSW data
if count = X"01FF" then -- 512 samples per rx period
State <= stStop;
else
State <= stIDLE;
end if;
AD7760_DATA24(7 downto 0) <= AD7760_D(15 downto ;
AD7760_STATUS24 <= AD7760_D(7 downto 0);
AD7760_SMPL_COUNT <= count;
AD7760_CS <= '1';
AD7760_DOUT_RDY <= '0';
delay <= 0;
end if; --delay

end case; --State
end if; --reset
end if; --rising_edge(AD7760_CLK)
end process; --AD7760_CLK40

end architecture;

[ivconic]

I would speculate that they are getting masked by viscous responses. Just a guess. You might be able to determine this by using a true all-metal threshold mode.
The differential preamp was posted in the TX thread, I don't see anything much better than that. Otherwise, the AFE needs some minor low-pass filtering and an ADC. Power supply is TBD but won't be esoteric. TX has also been posted. There isn't much more to it than that other than micro, audio driver, and display. But, yes, when I feel like all the problems are either solved or at least understood then I will put together a formal schematic. No need to jump ahead until we're ready.

I can't find it!? The TX thread is fed up with parts of spice attempts. You can't call it schematic.
Because I don't deal with spice simulators and I can't decypher the whole scribble presented there.
My suggestion is to trasnlate "all that" what You think is alright to a real schematic, drawn in real schematic capture software.
And then place it on fixed space (usually first page of thread) and say "this is real anf final schematic of this and that".
Same goes to TX part. And every other part.
Otherwise this is a mess. One claims "i did this and it si good", another claims "i did it different ways and it is good", third claim "both methods are fine but i know better"... "i suggest this"... "i suggest that"....
Me, guys; i am lost. Therefore me annoying you here with constant demands.
You can't expect me or any other to join here and work something, first by spending huge ammount of timy by decipehring those scribbles and all that mess done by now.
No order, nothing. Just a mess.
Extract most accurate version of schematics and place them on one fixed place and then say "this is what you need to join the work done by now".
...
Otherwise; there will only be a few of you klingon speakers working on this project because this is definitely not the way electronics are done so far.
I'm slowly getting the idea that a few of you are doing all this on purpose. In order to reduce the number of interested parties.
If it is like that; it is fairer to say so. Lock this thread and only allow "Klingons" to participate.

[ivconic]

..it will get there .. no point publishing schematics of a moveable feast. Some projects are designed in a cathedral and some in a bazaar .... I am more the walk around the bazaar and change my mind 20 times but I will go back to the best shops.
In the cathedral its all done by the numbers and everyone wearing strange clothes.

Stuff is happening .. I have dug out my FPGA bread board and it has a 2.5 MSPS AD7760 ADC on it ... I have already tested the CC transmitter on a VLF coil and it seems to work fine... but obviously will need DSP .. I already have the HDL code for the ADC to talk to the FPGA.

From a modular point of view it is coming together and everything is translatable to different hardware if needs be.

Once the building blocks are tied together the hardware can be finalised.

moodz

FPGA ... really!? Seriously!?

[Olly]

Stuff is happening .. I have dug out my FPGA bread board and it has a 2.5 MSPS AD7760 ADC on it ... I have already tested the CC transmitter on a VLF coil and it seems to work fine... but obviously will need DSP .. I already have the HDL code for the ADC to talk to the FPGA.

From a modular point of view it is coming together and everything is translatable to different hardware if needs be.

Once the building blocks are tied together the hardware can be finalised.

moodz

Very cool Moodz, I've got the exact same AD7760 evaluation board and am coupling it with a CMOD A7-35T (Artix 7) FPGA board to follow along with this experiment.
My HDL code is written in Verilog not VHDL like yours but both work just as well.
Looking forward to porting the DSP (once the concept is finalised) to the Artix as it has a number of high performance DSP blocks which should be just the ticket.

Olly