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Uuh! - Synthesizing VHDL ... brings back bad memories.
It does exercise the problem solving areas of the brain and impedes brain cell atrophy! At this stage in life, I need all the help I can get!
But seriously, the best solution will use both FPGA processing and uPC with a high resolution ADC (24 bit), with the FPGA taking care of timing and filtering and the uPC taking care of the analysis and determination of the data. With a 24 bit ADC we can sample a 500uH coil at 2.5 - 3us; a 2000 uH coil at 9 - 10usec easily and still have a LSB resolution of 250 nV and 115+ db dynamic range.
It does exercise the problem solving areas of the brain and impedes brain cell atrophy! At this stage in life, I need all the help I can get!
But seriously, the best solution will use both FPGA processing and uPC with a high resolution ADC (24 bit), with the FPGA taking care of timing and filtering and the uPC taking care of the analysis and determination of the data. With a 24 bit ADC we can sample a 500uH coil at 2.5 - 3us; a 2000 uH coil at 9 - 10usec easily and still have a LSB resolution of 250 nV and 115+ db dynamic range.
Where is the start time for the 2.5-3usec? reply #16 link above
The statement was not really in relation to the impulse circuit with a balanced co-planer,but a typical PI monocoil setup. With a 24 bit ADC with a 4.5 - 5V REF, a unity gain pre-amp feeding a ADC driver, you can sample when the coil voltage is at 2.5 to 3 V and still have your full dynamic range. That is where the 2.5 - 3 usec (after TX off) for a 500 uH coil and 9-10 usec for a 2000 uH coil comes from. In the impulse circuit it would be where the clamped discharge voltage waveform of the TX reaches 2.5 to 3V. The exact time would deprend on coil resistance and exact coil inductance since that effects the clamped discharge current until it is below the diode bias point. In the configuration of the link you provided, it would be ~36 -36.5 usec.
Mdtoday, Currently the project is in a status of suspension . I successfully proved the digital integration method using CIC filters implemented in the FPGA, feasibility of capturing/saving of the normal no target response, subtracting the no target response from the received signal to obtain a linearized response (i.e. target signal minus normal decay and ground response). I did not get around to the automatic setting of the optimal 1rst sample point, or the variable controls for timing, filter selection for automatic ground balance, etc. Also did not yet implement CFAR (Constant False Alarm Rate) for threshold.
Since I had started the project, I obtained a Vallon MH3CS. This unit does all of the things that the project was intended to address, thus why continue the project... spend my time using the Vallon. I still believe that to achieve the next level of performance from PI detectors using digital processing, you are going to have to incorporate FPGAs. There just isn't enough time/cycles to digitally processes signals with sequential processing. The nature of FPGAs allows concurrent processes to handle all of the signal processing while allowing to use your sequential processor to implement the User Interface. Digital processing of the signals provides the capability to do things that you could not do in analog, but to achieve them you have to stop thinking analog... more to multi dimensional thought processes and understanding.
But the end result is that since I never intended the process to invent and produce a new detector... just prove out some concepts, and that the Vallon serves my needs, the project will probably remain suspended until I have another area that I have to gain understanding of by experimentation. Also I have moved my FPGA experiments to the Xilinx Artix 7 development board.
Since I had started the project, I obtained a Vallon MH3CS. This unit does all of the things that the project was intended to address, thus why continue the project... spend my time using the Vallon. I still believe that to achieve the next level of performance from PI detectors using digital processing, you are going to have to incorporate FPGAs. There just isn't enough time/cycles to digitally processes signals with sequential processing. The nature of FPGAs allows concurrent processes to handle all of the signal processing while allowing to use your sequential processor to implement the User Interface. Digital processing of the signals provides the capability to do things that you could not do in analog, but to achieve them you have to stop thinking analog... more to multi dimensional thought processes and understanding.
But the end result is that since I never intended the process to invent and produce a new detector... just prove out some concepts, and that the Vallon serves my needs, the project will probably remain suspended until I have another area that I have to gain understanding of by experimentation. Also I have moved my FPGA experiments to the Xilinx Artix 7 development board.
Hi KingJL,
Thanks for the response. I fully understand where you are coming from. I've been there too with my MPI and another detector project that used FPGA but then I read Eric's post on the Vallon and decided that's the way to go, so purchased one.
A lot less hassle and much more fun using and modding the Vallon as time can disappear when we stick our heads into long term projects and leave no time for actually using what we make..
I was just reading over old posts and how many projects get completed or put aside (for whatever reason) and then I came across yours again and it made great reading so I wondered if you had shelved it etc.
I work with DSP and FPGA hardware on a daily basis and agree with your views. Was also looking at some Artix 7 boards last night, they have certainly come down in price and increased features.
Anyway, thanks for your reply and good hunting with your Vallon, they are a great detector.
With a 24 bit ADC with a 4.5 - 5V REF, a unity gain pre-amp feeding a ADC driver, you can sample when the coil voltage is at 2.5 to 3 V and still have your full dynamic range.
In my experience, sampling on top of the transient causes falsing because of 1/f or flicker noise.
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