I'm not sure which version of the Baracuda schematic you are all looking at, but it would appear that the CD40106 should have its VCC pin connected to GND, and its VSS pin connected to -5V.
The reason being that the 2N5485 sample gates are N-channel JFETs. This means that when the JFET is conducting (on) the gate has 0V applied, and is off when the gate is in reverse bias (i.e. at -5V).
Basically, the original circuit looks ok to me.
The reason being that the 2N5485 sample gates are N-channel JFETs. This means that when the JFET is conducting (on) the gate has 0V applied, and is off when the gate is in reverse bias (i.e. at -5V).
Basically, the original circuit looks ok to me.
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